A new method for tolerance test of high-speed serial signal receiving end based on digital synthesis technology

Introduction

During the verification of a system or chip, the receiver test of a chip using a high-speed serial signal standard requires an excitation signal source. Designers have always relied almost entirely on digital signal generators to generate binary signals for serial testing. They use input signal amplitude adjustment, jitter injection, phase offset adjustment and other means in digital signals to simulate a relatively harsh working environment to test the receiving tolerance of the receiving end. However, new technologies in the field of signal sources are changing all this. Direct synthesis tools can help designers create more realistic signals and greatly reduce the measurement errors that may be introduced by complex test settings and multiple equipment sharing.

The significance of generating signals by direct digital synthesis

Serial signals are composed entirely of simple binary numbers 1 and 0. Why use direct digital synthesis analog waveforms to represent digital data? This is because analog events are implicit in digital signals. The zero rise time and perfect "flat top" of ideal digital signals in books are virtual. The actual working environment has noise, crosstalk, reflections, power supply changes and other shortcomings, each of which will affect the signal. The advantage of direct synthesis signal source is that it can completely "imitate" the analog characteristics of the actual signal, and can arbitrarily control the signal's rise time, pulse shape, delay, distortion, jitter change law, etc., which is exactly what is required for strict serial bus testing. Tektronix's AWG7000 is an arbitrary waveform generator that uses direct digital synthesis to generate signals. It can generate a test signal with all the required timing, amplitude and distortion characteristics, rather than first generating a "clean" ideal signal like a general digital signal source, and then degrading the signal through various combinations to simulate the real environment.

Analog characteristics of high-speed serial signals in actual working environments

Due to the attenuation and reflection of the transmission medium, the signal will degrade to varying degrees, which is specifically manifested as increased jitter and attenuation of signal amplitude. In actual working environments, as the signal rate increases, the influence of the transmission medium on the signal becomes more and more obvious, and the signal generally degrades in proportion to the signal rate and the length of the transmission path. In large-scale engineering production and manufacturing processes, the performance of PCBs, connectors, and cables may be sacrificed in exchange for cost advantages, which further increases the tolerance requirements of the receiving end.

Due to the jitter of the clock chip, the fluctuation interference of the power plane, and the crosstalk of low-frequency but high-energy signals around the serial signal, these will cause the serial signal to change in timing. This change is manifested as the jitter of the signal edge changes regularly with the change of the interference signal; or in order to reduce the radiation of EMI, a low-frequency modulation is deliberately superimposed on the clock signal, so that the frequency of the signal increases or decreases regularly with the modulation signal, and the spectrum is spread over a relatively wide frequency range, while reducing the peak value of the spectrum, which is generally called SSC (spread spectrum clock).

In order to reduce the waveform distortion and the increase of ISI jitter components caused by the attenuation of the transmission medium, and improve the signal integrity during the transmission process. The industry generally uses de-emphasis technology to compensate for the attenuation of high-frequency components by the transmission line and improve the signal fidelity at the receiver input. However, the response of the serial device to de-emphasis must be fully evaluated during the design phase. During the debugging process, the de-emphasis ratio can be adjusted according to the actual situation to obtain the best transmission effect.

Methods for simulating serial signal characteristics by traditional digital signal sources

General digital signal sources can simulate digital signals with relatively simple regular changes, such as signals containing random noise, or signal jitter changing with a single sine law or triangular wave law. This can be achieved by using multiple instruments to mix and inject jitter and noise of different characteristics. However, if the degradation of the signal is irregular or changes with a more complex law, such as jitter caused by power supply or other high-energy signal interference in the sinusoidal jitter, it is difficult for the digital signal source to simulate.

Figure 1: Method for digital signal source to achieve "de-emphasis" characteristic signal

To realize the "de-emphasis" feature commonly used in serial signal standards, the digital signal source needs to use multiple channels and power combiners for complex connection, and the phase relationship of multiple channels must be accurately controlled, otherwise the obtained signal will be very different from the expected one. The principle is shown in Figure 1. Delay CH1 by one bit (UI) relative to CH2, and then subtract the two channels to obtain the de-emphasized signal in Figure 1.

How to simulate serial signals using AWG (arbitrary waveform generator) based on direct digital synthesis principle

Direct synthesis is a sampling-based technology. A direct synthesis signal source (AWG) creates analog waveforms from samples. Within the range of bandwidth and sampling rate, the samples in the AWG memory can basically define any waveform. These samples can be obtained from the actual waveform collected by the oscilloscope, or they can be arbitrarily defined by formulas or algorithms.

Figure 2 Direct digital synthesis signal source simulation method for serial signal

In addition to being able to synthesize signals with any jitter pattern or noise, establish the impact model of random jitter and deterministic jitter, and change the applied effect in a quantitative and qualitative way, the direct synthetic signal source can also simulate the distortion of signals such as attenuation, reflection, and crosstalk caused by the different characteristics of specific media during transmission. In addition, there is no need to use complex external equipment to inject jitter or noise. All signal characteristics are synthesized in the processor and memory of the instrument, so the connection is very simple, and it can reduce the errors or uncertainties that may be caused by the interconnection between instruments, as shown in Figure 2.

The rate of the synthetic signal, the frequency and amplitude of the jitter injection, the amplitude of the noise, and the rise time of the signal can all be defined quickly and conveniently through Tektronix's SerialXpress software, and the effect can be simulated in real time, as shown in Figure 3.

Figure 3 Using SerialXpress software to define serial signal characteristics

The direct synthesis method for de-emphasized signals is completely different from the digital signal source, but the results are exactly the same. The signal stored in the AWG already contains the "de-emphasis" feature, so there is no need to generate and externally combine two data streams to obtain a synthesized signal. The output of a single channel can be achieved as shown in Figure 4. Moreover, the "de-emphasis" ratio, such as -3.5dB, -6dB, etc., can be adjusted arbitrarily as needed.

Figure 4: Simulation method of the “de-emphasis” characteristic of a direct digital synthesis signal source for a serial signal

Application of Direct Synthesized Signal Source (AWG) in the Current Popular Serial Bus Compliance Test

1 Compliance Test of SATA Bus

Currently, SATA Workgroup has released the consistency test specifications and implementation methods for the transmitter, cable and receiver. The jitter tolerance consistency test of SATA receiver requires the DUT to enter loopback mode. When the device is in this mode, the test instrument (signal source) sends a jitter-containing signal to the receiver of the DUT, and then the transmitter of the DUT will respond correctly to the received signal. Finally, the error frame detector (Frame error detector) detects whether the data output by the DUT transmitter is correct, or the jitter amplitude injected by the signal source can be gradually increased until the Frame error detector detects the occurrence of an error frame. The jitter amplitude obtained at this time is the jitter tolerance value of the receiver. Traditionally, special application software needs to be run on an external PC to force the DUT into loopback mode. Unfortunately, once the signal source is disconnected, most transceivers will automatically exit the loopback mode and return to normal operation, so the test cannot be continued. A common solution to this challenge is to send BIST-L commands to the DUT through a power synthesizer, as shown in Figure 5. By using a power combiner in the test circuit, the data generator can start sending test data to the DUT when loopback mode is activated, without requiring disconnection. Power combiners are a viable solution, but they have their drawbacks. Obviously, they increase complexity and the chance of connection errors, poor electrical contacts, and other mechanical problems; they also require calibration of all input sources to ensure that jitter components are properly introduced. Most importantly, power combiners can attenuate the data signal voltage by up to 50%.

Figure 5 Method for implementing jitter tolerance test of SATA receiver using digital signal source

If the AWG direct synthesis method is used, the instrument can send loopback commands instead of the PC. It does not require a power synthesizer or a PC running BIST-FIS software. Figure 6 shows a jitter tolerance test system based on AWG: one instrument generates the input signal and one instrument reads the output. As can be seen from the SATA test configuration, it is very simple and convenient to build a test environment using the direct digital synthesis method through AWG.

Figure 6 Direct digital synthesis signal source to achieve SATA jitter tolerance test method

2 DisplayPort bus compliance test

In the jitter tolerance test of the receiver of Display Port Compliance Test Specification Version1, the signal source is required to provide signals containing different jitter frequencies, jitter amplitudes and jitter components, which are input to the receiver of the sink, and then the bit error rate of the sink is observed to test the performance of the receiver. This is a challenge for traditional digital signal sources. Please see the solution of traditional digital signal sources in Figure 7. In order to synthesize complex jitter components, an additional noise signal generator and vector signal generator are required, and both need to be synthesized with a power divider to inject jitter into the digital signal source. The construction of the entire test environment is very complicated. The unique advantage of the direct synthesis signal source implementation method in Figure 8 is that it only needs to press one key to output the synthesized signal. These signals include sine, ISI, Rj, Pj jitter, pre-emphasis, balance, jump time and amplitude control. The connection is simple and the test consistency and repeatability are very high.

Figure 7 Method for implementing jitter tolerance test of DisplayPort receiver using traditional digital signal source

Figure 8 AWG's method for implementing DisplayPort jitter tolerance testing using a direct digital synthesis signal source

3 HDMI Conformance Test

In the HDMI CTS1.3b specification, in addition to adding two frequencies of jitter in the Sink jitter tolerance test, it is also required to add TTC (transition time converter) and Cable emulator to ensure that the signal rise time and jitter components meet the specification requirements. The digital signal source is implemented in the way shown in Figure 9.

Figure 9 Method for implementing jitter tolerance test of HDMI receiver using digital signal source

For TTC, different TTCs are required to be added at different test frequencies, namely: 74.25MHz/450ps, 148.5MHz/220ps, 165MHz/200ps, 222.75MHz/150ps, and 340MHz/60ps. For Cable emulator, it is also required to use 5 cable emulators with different characteristics at different test frequencies.

According to the specification, the test of Sink needs to test its performance at different clock frequencies. This may lead to frequent replacement of different TTCs and Cable emulators during the test. In addition to spending a lot of time, it may also lead to test differences caused by factors such as poor signal contact caused by frequent changes in connections. In addition, since Cable emulators and TTCs are expensive, additional large expenses are required. The signal is generated by directly synthesizing the signal, and the characteristics of TTC and Cable emulator can be simulated by AWG. As shown in Figure 8, whether testing DisplayPort or HDMI, it is convenient to use AWG with direct digital synthesis method to easily generate various high-speed serial signals with simple configuration.

in conclusion

Direct digital synthesis can create any standard high-speed serial signal, so that the generated signal has all the characteristics required for consistency measurement, limit testing and debugging, including multi-level signals, simple SSC clock modulation, complex jitter and signal distortion. This technology can greatly simplify the test connection while achieving good test consistency and repeatability. In the future signal integrity test of various high-speed serial data, this signal synthesis method is being adopted by more and more serial signal test standard committees.