A New Method for Wafer-Level 1/f Noise Measurement

1. Introduction
MOSFETs are widely used in analog and RF circuits. However, low-frequency noise in MOSFETs, especially the higher frequency 1/f noise, is an important factor of concern in analog and RF circuit applications. In addition, as the device feature size decreases, the 1/f noise will increase significantly [Reference 1]. Therefore, it is very necessary to design a reliable, repeatable, and accurate measurement method and system when measuring 1/f noise. In the past few
years, many 1/f noise measurement schemes and configurations have been studied. For example, a configuration scheme appeared in 1990 [1]. This configuration uses an SMU and two low-pass filters to bias the drain and gate. The noise in the drain is detected by a preamplifier and a dynamic signal analyzer. The second configuration is similar to the first one, except that a battery is used to provide the bias. In the third solution [2], several key components such as low noise amplifiers (LNAs), cascaded diodes, and filters are used. However, these existing measurement configurations can only measure noise in the higher frequency band (for example, above 100Hz).
This paper proposes a new reliable wafer-level 1/f noise measurement method and corresponding test architecture, which can measure low-frequency 1/f noise below 100 Hz.
1. Noise model
There are many theoretical explanations for the origin of 1/f noise, such as Whorter's carrier fluctuation theory[*], Hooge's mobility fluctuation theory based on experimental results[*], and a unified noise model that combines the two[1]. In 2003, Wong published a review paper on 1/f noise research and recent progress[2].
Although Hooge's experimental results are consistent with the model in some cases, Whorter's theory is usually used to simulate MOSFET's 1/f noise. For example, the noise model in the commonly used simulation software HSPICE is based on Whorter's theory. Table 1 shows the noise model in HSPICE.
Table 1. HSPICE representation of 1/f noise in MOSFETNLEV
=0 NLEV=1 NLEV=2Noise
model

(1) Based on this equation, a log-linear equation at a fixed frequency can be derived: (2) The goal of the new measurement method and architecture is to extract the parameters AF and KF in the equation. These two parameters can change the frequencies in the power spectrum that are extracted. 3. Measurement Architecture a) Noise Measurement Configuration The noise measurement configuration is made up of a series of measurement instruments from Keithley , including the Semiconductor Characterization Analysis System KI4200-SCS, the Programmable Low Current Amplifier KI428-PROG and the Low Pass Filter, and Keithley ’s ACS (Automated Characterization Suite) software. When building this configuration, special attention was paid to minimize external electromagnetic noise. The schematic diagram of the test configuration is shown in Figure 1, where the dashed lines represent the ACS control flow and the solid lines represent the data flow.

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b) Test system design
KI 4200-SCS and KI 4200-SCP2 with ACS software installed can provide input voltage, control current-voltage measurement, measure noise signal, control current amplifier, and analyze test results.
We use a KI 4200 SMU and a 0.5Hz filter to provide the input bias of the device. Since the low-pass filter can eliminate all noise above 0.5Hz, the accuracy of 1/f noise measurement is greatly improved. The filter is shielded with a metal box to avoid the introduction of external electromagnetic interference, so that the input bias is as DC bias as possible.
A probe station is used to measure wafer-level 1/f noise. The probe station, DUT (device under test) and filter are all shielded with electromagnetic shielding metal boxes, thereby eliminating and reducing the interference of external noise. The
low current amplifier KI 428-PROG plays an important role in 1/f noise measurement. KI 428-PROG is powered by an internal battery, so that in addition to amplifying the current noise of the DUT, it can also provide bias voltage at the output of the DUT. The output of the DUT is directly connected to the input of the KI 428-PROG. The KI 428-PROG can provide an output voltage ranging from -5V to 5V with a resolution of 2.5mV. Therefore, we can bias the DUT at the required voltage to prevent it from being interfered by the noise of the AC line. The gain of the KI 428-PROG can be adjusted in the range of 103 to 1011. Since the KI 428-PROG is equipped with a GPIB port, the ACS software can program it through the IEEE-488 bus. The 428-PROG can make the device work in different areas by combining different bias voltages.
The KI 4200-SCP2 is connected to the output of the current amplifier. The KI 4200-SCP2 is a dual-channel digital storage oscilloscope with an embedded digital signal processor. Therefore, under software control, this oscilloscope can monitor, capture and analyze the output signal.

c) Software Control
The ACS (Automatic Characterization Suite) software platform supports cassette-level, wafer-level, and device-level semiconductor characterization analysis using a variety of test instruments, and supports automated parameter testing based on semi-automatic and fully-automatic probe stations. After being installed on the Keithley 4200-SCS, it controls the 4200-SCS or external measurement instruments through the GPIB interface. Since the KI-428 has a GPIB control port, an automated noise measurement system can be implemented. We coded all the test routines into a test module. This module can be copied in the ACS test environment. By setting a series of test modules under different conditions, ACS is able to provide a variety of different test modules. Using modules belonging to the same device, they can be tested at the device level. 4. Verification and Discussion To verify the above test architecture, we analyzed and evaluated the 1/f noise characteristics of nMOS and pMOS devices of different sizes under various bias conditions and compared them with the simulation results. Figure 2 shows the measurement results of the drain current noise of the p-type MOSFET. The left figure shows the noise current signal captured by KI 4200-SCP2 under the control of ACS software over 20 average measurement cycles. The right figure is obtained by fast Fourier transforming these measured data, which clearly shows that there is a 1/f correlation between the current noise spectrum of the drain and the frequency.

Figure 2. Drain current noise measured for a pMOS tube
As mentioned above, our measurement goal is to extract the noise parameters AF and KF. In order to extract AF and KF, it is necessary to measure the current noise under different bias conditions. Figure 3 shows the measurement results of a pMOS tube under different bias conditions.

Figure 3. Noise data measured at different gate bias voltages [page]

In order to analyze the gate oxide capacitance correlation or conduct other further research, we also measured the 1/f noise under different gate oxide thicknesses. Figure 4 shows the test results under different gate oxide thicknesses.

Figure 4. 1/f noise measurement data of pMOS devices with different gate oxide thicknesses
Then, we can estimate the 1/f noise parameters and build different simulation models. Figure 5 shows the drain current noise power measured in the strong inversion region of a p-channel MOSFET.

Figure 5. Relationship between drain current 1/f noise and gate bias voltage
5. Conclusion
This article introduces a wafer-level measurement method and configuration scheme for evaluating MOSFET 1/f noise. This measurement technique can be performed automatically on the wafer. Since this configuration scheme can measure low-frequency noise components below 100Hz, it can effectively extract the MOSFET 1/f noise.