Multi-channel synchronous data acquisition and compression system

1 Introduction
In order to minimize the transmission time and storage space in modern telemetry systems and transmit more useful information within the limited channel capacity, data compression technology is used to help reduce power and bandwidth requirements and improve communication efficiency. Here, a design scheme for a multi-channel synchronous data acquisition and compression system based on DSP and CPLD is proposed. The system is applied to telemetry multi-channel noise data, in which multi-channel synchronous data acquisition can realize simultaneous measurement of signals. After correlation analysis, the relevant information between signals is obtained, and the data compression algorithm embedded in the DSP realizes its data compression function.

2 Hardware structure of the system
2.1 System design ideas
Figure 1 is the hardware block diagram of the system design. The multi-channel synchronous data acquisition and compression system based on CPLD and DSP is mainly composed of three parts: data acquisition module, data processing module and data interface module. The analog signal input by the sensor at the front end is shaped and amplified by the signal conditioning module, and then input into the A/D conversion module. The analog quantity is converted into digital quantity. The programmable logic device (CPLD1) controls the A/D converter to collect data according to the set sampling rate and write the collected data into the FIFO through the bus. When the FIFO is half full, a half-full signal is sent, that is, the interrupt of the DSP. After receiving the interrupt, the DSP immediately reads a frame of data from the FIFO to the data processing module. The DSP compresses the collected data at high speed and writes it into the interface module. Then the programmable logic device (CPLD2) transmits the data to the telemetry system through the RS-422 bus for further analysis.

2.2 Device Selection
2.2.1 A/D Converter ADS8365
The A/D conversion module of this system uses TI's ADS8365 A/D converter, which supports 6-channel signal differential input, has 3 groups of signal acquisition control terminals, each group controls 2 signals, 16-bit accuracy, and the conversion speed of each channel is up to 250 kHz. It supports high-speed parallel data output interface, and the data output interface includes direct address selection mode, CYCLE mode, and FIFO mode.
2.2.2 Complex Programmable Logic Device (CPLD) XCR3256XL
uses CPLD to control each interface. Here, XCR3256XL CPLD is selected. It is a high-performance complex programmable logic device (CPLD) of Xilinx's CoolRunner series. The device has the following features: using COMSEEPROM manufacturing process technology; built-in standard JTAG interface, supporting 3.3 V in-system programmability (ISP); 3.3 V power supply, integration density of 6 000 available gates; pin-to-pin delay of 7.5 ns. The system frequency is up to 140 MHz. Compared with separate logic devices, the single-chip CPLD realizes the logic control function, simplifies the circuit design, and improves the system reliability. In addition, XCR3256XL has the function of in-system programming. It only needs a download cable to connect to the target board, which can easily realize multiple repeated programming, greatly facilitating circuit debugging.
2.2.3 Digital Signal Processor (DSP) TMS320C6713B
The DSP designed in this system uses TMS320C6713B, which is one of the TMS320C67xx series floating-point DSPs launched by TI. It adopts an improved Harvard structure, which has the characteristics of fast operation speed, low power consumption and high cost performance. Its architecture adopts the Veloci TI Very Long Instruction Word VLIW (Very Long Instruction Word) structure. It executes 8 32-bit instructions per cycle and supports 32/64-bit data. It adopts RISC-like instruction set, has an operating speed of 300 MHz, 3.3 ns instruction cycle and a processing capacity of 2 400 MI/s or 1 800 MFLOPS, which is suitable for high-speed signal processing. In order to speed up the processing speed, the DSP core adopts a 2-level cache, of which the L1 level cache is divided into 4 KB direct program cache and 4 KB data cache (divided into 2 ways); the L2 level cache is divided into 64 KB unified memory and 192 KB additional memory. It has a 16-channel EDMA controller inside, which can handle almost all I/O and memory interface problems at high speed, greatly improving the device throughput. The maximum total external memory address space is 512MB, the data width is 32b, and it can support SBRAM, SDRAM, SRAM, Flash and EPROM. The TMS320C6713 and the external I/O interface are realized through the I/O port constructed by FFA, HPI port, multi-buffered serial port (McBSP), SPI port and other methods. Compared with dedicated hardware compression devices, TMS320C6713B can easily realize data compression. And the system upgrade and configuration are flexible. [page]

3 CPLD Part Design
3.1 CPLD1 Control Part
CPLD1 controls ADS8365, including controlling the sampling rate of the A/D converter and the data quantization output mode, and controlling the CS signal can effectively suppress noise; the system clock input is 50 MHz, and CPLD1 divides it to generate a 5 MHz clock to trigger the A/D converter. The program starts the A/D conversion by controlling the HOLDX of the A/D converter; controls the ADD of the A/D converter to control its output channel information, and controls the ADDRESS of the A/D converter to control its data output working mode. Considering that the program algorithm in the DSP will increase the DSP calculation burden every time it determines the channel information, the A/D conversion is set without channel information, and the A/D converter works in the CYCLE mode. The data after A/D conversion is cyclically output in the order of channel numbers, and the DSP can directly determine the specific channel of the data according to the sequence. Figure 2 shows the circuit of CPLD1 controlling ADS8365.

CPLD1 controls DSP, including DSP reset setting, watchdog setting, DSP control signal and CE space combination logic control reading FIFO1, etc.
3.2 Data frame format setting
CPLD1 continuously writes the data after A/D conversion into FIFO1. When 2 048 bytes of data are written into FIFO1, CPLD adds a 16-bit frame flag and a 16-bit frame count, that is, the data format is: collected data + frame flag + frame count.
3.3 CPLD2 control interface
The core of the interface conversion module is CPLD, which is responsible for reading data from the output FIFO2 and encoding it according to the timing requirements of the telemetry system. The compressed data is uploaded to the telemetry system through the RS-422 bus.

4 DSP Partial Design
4.1 DSP Program Design Process
After the device is powered on and the DSP is reset, the internally fixed self-boot program (BOOT) moves the program and data stored in the Flash memory to the internal RAM, and then the DSP starts to read the application program of the compression algorithm and continues to run. The workflow of the DSP is: first initialize the CSL function library of the DSP, then initialize the PLL, GPIO and related interrupt registers, and wait for interrupts. The
16-bit data of the acquisition module is continuously written through the bus. FIFO1. The program controls its half-full (HF) signal, that is, when the data exceeds half full, the HF signal is low-level valid, which will trigger an interrupt to notify the DSP. After the DSP enters the interrupt, it reads 2048 bytes of data from the input FIFO1 into the SDRAM space pointed to by the DSP. The DSP performs high-speed compression in the idle time after processing the interrupt. Compare the compressed data with the original data. If the compressed data is smaller than the original data, the compressed data is written into the soft FIFO of the DSP. Otherwise, the original data is written into the soft FIFO of the DSP.
Finally, DSP writes the compressed data in the soft FIFO into the output FIFO2, waiting for the sending module to upload the data to the telemetry system.
4.2 Data compression algorithm selection
The compressed coded source information can be completely restored during decompression, that is, the source information is not lost during the compression and decompression process. This coding method is called lossless compression. Commonly used lossless compression methods include Shannon-Fano coding, Huffman coding, run-length coding, IZW (Lempel-Ziv-Welch) coding and arithmetic coding (ARC). Here we focus on the ARC algorithm and the LZW algorithm. The idea of ​​the ARC algorithm is like looking up a dictionary. As we all know, the arrangement of English dictionaries is in alphabetical order, and words with the same first letter continue to be sorted by the second letter, and so on. The actual application of arithmetic coding is more clever. The probability of the occurrence of characters is used to divide the interval from 0 to 1, and then a decimal between 0 and 1 is used to encode the data. The more original data, the more digits after the decimal point.
LZW coding is completed around a conversion table called a dictionary. The conversion table is used to store character sequences called prefixes, and a code word, or serial number, is assigned to each table entry. This conversion table actually expands the 8-bit ASCII character set. The added symbols are used to represent variable-length ASCII strings that appear in text or images. The expanded code can be represented by 9 to 12 bits or even more. There are 4,096 different 12-bit codes for 12 bits, which means that the conversion table has 4,096 entries, of which 256 entries are used to store defined characters, and the remaining 3,840 entries are used to store prefixes. The LZW encoder (software encoder or hardware encoder) completes the conversion between input and output by managing the dictionary. The input of the LZW encoder is a character stream, which is a string composed of 8-bit ASCII characters, and the output is a code stream represented by n bits (for example, 12 bits). The code word represents a single character or a string composed of multiple characters. The LZW encoder uses a practical parsing algorithm, called the greedy parsing algorithm.
In the greedy parsing algorithm, each analysis serially checks the string from the character stream, decomposing the longest recognized string, that is, the longest prefix that has appeared in the dictionary. The known prefix is ​​added to the next input character C, that is, the current character, as the extension character of the prefix to form a new extended string - Sning: Prefix. C. Whether this new string is to be added to the dictionary depends on whether there is a string that is the same as it in the dictionary.
If so, then this string becomes a prefix, and new characters continue to be input. Otherwise, this string is written into the dictionary to generate a new prefix and given a code.
In general, different compression algorithms have different advantages and disadvantages. The complexity of different algorithms also has different space requirements and compression rates. This depends not only on the compression method, but also on the characteristics of the compressed data.

[page]

The system is designed to compress real-time data, which requires a high time performance of the compression process, so the ARC algorithm with a pre-statistical model is used. Experiments have shown that the operation speed of this algorithm is similar to that of the LZW algorithm. The ARC algorithm is superior to the LZW algorithm in terms of compression removal rate.

5 Experimental results
The algorithm selection is mainly compared from the compression speed and compression removal rate. In this design, the front end collects multi-channel noise compression of a system in real time at a speed of 27 kHz. From Table 1, it can be seen that the data compression removal rate of the ARC algorithm for different grouping segments is about 79%, while the LZW algorithm has a compression removal rate of only about 31% in this grouping segment. It can be seen that the compression removal rate of the ARC compression algorithm is relatively high. In the experiment, a certain regular data is sent through the host computer, and the compressed data is processed by the system. The compressed data is then unpacked and decompressed by the host computer, and the restored data is compared with the original data. The results are consistent, proving that the system is safe and reliable. Figure 3 is the host computer decompression report.

6 Conclusion
The system composition is introduced in detail, and the architecture of complex programmable logic device (CPLD) and digital signal processor (DSP) is used to compare the related algorithms of lossless compression, and finally arithmetic coding (ARC) is used as the system compression algorithm. The innovation of this system lies in the multi-channel synchronization of the acquisition module and the pertinence of noise data compression. Finally, through a large number of experiments, it is confirmed that this scheme is feasible and all indicators meet the system requirements.