Technical Articles | FAQs on Common DC-DC Applications (Part 1)
This issue of SCT summarizes and sorts out the power management chip issues that engineers often encounter when selecting and testing, so as to quickly answer everyone's questions. Experts are welcome to add discussion questions and answers in the message area .
Table of contents
1
Why is the measured value of static current IQ on the board different from the nominal value in the chip specification?
2
What are the differences, advantages and disadvantages of PSM (PFM), USM and FPWM (FCCM)? Why do some DCDCs have inductive howling?
3
Chip Vin_UVLO meaning
4
How to avoid power-on and power-off oscillation problems when designing EN enable logic?
5
Soft-start solves problems such as overshoot and overshoot at power-on and inability to start the electronic load under heavy load.
6
How to understand thermal resistance parameters and calculate chip junction temperature through thermal resistance?
01 Quiescent current I Q , why is the measured value on the board different from the nominal value in the chip specification?
The nominal value of the static current IQ specification is tested and defined for the chip unit. It is the value when the MOS inside the chip is not working (non-switching state) and only the chip logic circuit is in standby state .
On a single board, after the chip works normally, the normal switching of the MOS inside the chip will cause switching loss and drive loss, and peripheral devices such as inductors, EN pin voltage divider resistors, and FB feedback resistors will all have losses .
Therefore, even in the absence of load, the quiescent current on the board will be greater than the value defined in the chip specification .
Taking SCT2450Q as an example, the chip I Q is 25uA. After the demo board is powered on, the no-load input current of the circuit is about 80uA.
02 What are the differences, advantages and disadvantages of PSM (PFM), USM, and FPWM (FCCM)? Why do some DCDCs have inductive howling?
Taking SCT2A23 (100V/ 1.2A synchronous rectification) as an example, there are three working modes to choose from. The differences between different working modes are shown in the figure.
03 Meaning of chip Vin_UVLO
UVLO Rising Threshold is the chip startup voltage , that is, when the input voltage rises to this voltage value, the chip starts working;
Hysteresis is the hysteresis, that is, when the chip starts working normally, if the input voltage drops to VULO_Rising-Hysteresis, the chip stops working .
For example, SCT61240Q has a rising voltage of 3.8V and a hysteresis of 0.2V, that is, the chip startup voltage (Von) is 3.8V and the chip shutdown voltage (Voff) is 3.6V.
04 EN enable design logic, how to avoid the power-on and power-off oscillation problem?
EN is mainly used for chip enable control. When the input voltage is ≥ UVLO voltage, the chip can be powered on and off through EN . At the same time, the startup voltage (Von) and shutdown voltage (Voff) hysteresis can be set to ensure that the chip will not have a false switch problem near the startup critical point voltage in any case . Effectively solve the voltage rebound and oscillation problems caused by load release during the power-off process.
EN design logic:
1. V out > UVLO, V off voltage set by EN > V out ;
2. V out ＜UVLO, V off voltage set by EN ＞UVLO;
3.V hys > chip V in _UVLO_Hysteresis;
Taking SCT2A00 (100V/0.6A DC-DC) as an example, the calculation formulas for setting V on and V off through EN are as follows:
According to the calculation formula: the larger the EN pull-up resistance, the greater the hysteresis, and the less likely the chip will restart repeatedly due to the input voltage rebound; the EN ground resistance value selection recommendation is less than Vin_fall/(I1+I2);
05 Soft-start to solve problems such as overshoot and overshoot on power-on and inability to start the electronic load under heavy load
What is soft start
SS soft-start is to configure a startup time for the switching power supply circuit, which can make the output voltage rise monotonically to the target voltage value after startup.
The soft start time SS time is the time from when the output voltage starts to when it ends.
Soft start function
Soft-Start Capacitor & Timing Selection
Choose the appropriate value according to the application. The larger the capacitance, the longer the soft start time . The larger the capacitance, the longer the discharge time. If there is a rapid and repeated power-on and power-off scenario, the soft start capacitor is not fully discharged, and the soft start process is not performed when the power is turned on again, which may cause the output voltage to overshoot and other phenomena.
06 How to understand thermal resistance parameters and calculate chip junction temperature through thermal resistance?
The following table shows the typical thermal indicators of SCT2464Q (40V/6A BUCK, QFNFC4×3.5-14L Package)
RθJA
Definition : The thermal resistance of the junction to the environment under still air conditions . Heat is conducted through the package and has little to do with the PCB, such as some vertical package products.
Applicability : Used to compare the thermal performance of different devices in the same package type , not suitable for junction temperature estimation.
RθJC
Definition
: The thermal resistance between the junction and the case surface (top or bottom package), where all heat is conducted through a
single surface
of the device
(top of the case or bottom of the package).
Applicability : Applicable to situations where heat sinks are mounted only on the top or bottom of the package, where more than 90% of the heat is dissipated from the top or bottom .
For typical plastic packaged SMD devices without top heatsinking , estimating the junction temperature by simply measuring the case top temperature and calculating the device power dissipation is incorrect, which may result in an estimated value that is much higher than the actual junction temperature .
RθJB
Definition : The thermal resistance from junction to PCB (not the bottom of the package). PCB is the main path for heat dissipation of the device. Ensure that all heat flows to the PCB.
Applicability : JEDEC standard: FR4, 4-layer, 1.6mm thick high thermal conductivity PCB (High-KPCB) evaluation, top and bottom copper foil thickness 2oz, middle two layers 1oz; single board size is usually 11.4×7.6cm or 11.4×10.2.
If the PCB design in the actual application is similar or more optimized, this parameter can be used to estimate the junction temperature, TJ=TB+(θJB*P).
ΨJT/ΨJB
Definition : Thermal characteristic parameter, indicating the ratio of the temperature difference between the chip junction and the reference point to the total dissipated power .
Applicability : In practical applications, the heat conduction paths are diverse, and heat is conducted through multiple channels. The thermal characteristic parameter Ψ represents the ratio of the temperature difference between the chip junction and the reference point to the total dissipated power, which is more suitable for estimating the junction temperature and is more accurate . The commonly used junction temperature calculation method is: TJ=TC+(ΨJT*P).
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