If minimum noise yields diminishing returns, how much power supply noise is acceptable?

One might think that the noise generated in each power domain (analog, digital, serial digital, and digital input/output (I/O)) should be minimized or isolated to achieve excellent dynamic performance, but the pursuit of absolute minimum noise can lead to diminishing returns. How does a designer know if the noise performance of a power supply is adequate? It starts with quantifying the sensitivity of the device and matching the power supply spectrum output to the requirements of that power domain. Knowledge is power: saving design time by avoiding over-design can go a long way in helping a design.

This article provides an overview of how to quantify the power supply noise sensitivity of loads in a signal processing chain and how to calculate the maximum acceptable power supply noise. The measurement setup will also be discussed. Finally, some strategies for meeting power domain sensitivity and real-world power supply noise requirements will be discussed.

The first step in power supply optimization is to investigate and analyze the true sensitivity of analog signal processing devices to power supply noise. This includes understanding the impact of power supply noise on key dynamic performance specifications and characterizing the sensitivity of power supply noise—that is, power supply modulation ratio (PSMR) and power supply rejection ratio (PSRR).

PSMR and PSRR indicate good power supply rejection, but they alone are not enough to determine how low the ripple should be. This article shows how to use PSMR and PSRR to determine the ripple tolerance threshold or maximum allowable power supply noise. Only by determining the threshold that matches the power supply spectrum output can an optimized power system design be achieved. If you ensure that the power supply noise is below its maximum specification value, the optimized power supply will not degrade the dynamic performance of each analog signal processing device.

The effects of power supply noise on analog signal processing devices should be understood. These effects can be quantified using three measurement parameters:

• Spurious Free Dynamic Range (SFDR)

• Signal-to-Noise Ratio (SNR)

• Phase Noise (PN)

Understanding the effects of power supply noise on these parameters is the first step in optimizing power supply noise specifications.

Power supply noise can couple into the carrier signal of any analog signal processing system. The impact of power supply noise depends on its strength relative to the carrier signal in the frequency domain. One measurement is SFDR, which represents the smallest signal that can be distinguished from a large interferer—specifically, the ratio of the amplitude of the carrier signal to the amplitude of the highest spurious signal, regardless of where it is in the frequency spectrum, yielding the following equation:

SFDR = Spurious Free Dynamic Range (dB)

Carrier Signal = RMS value of the carrier signal amplitude (peak or full scale)

Spurious signal = the RMS value of the highest spurious amplitude in the spectrum

Figure 1. SFDR of the AD9208 high speed ADC using (a) a clean supply and (b) a noisy supply.

SFDR can be specified relative to full scale (dBFS) or relative to the carrier signal (dBc). Power supply ripple coupling to the carrier signal can create interfering spurious signals that degrade the SFDR. Figure 1 compares the SFDR performance of the AD9208 high speed ADC when powered from a clean supply and a noisy supply. In this case, the power supply noise degrades the SFDR by approximately 10 dB when the 1 MHz power supply ripple appears as a modulation spur near the carrier frequency in the ADC’s ​​fast Fourier transform (FFT) spectrum output.

SFDR is determined by the highest spur in the spectrum, while SNR is determined by the total noise within the spectrum. SNR limits the ability of an analog signal processing system to discern low amplitude signals and is theoretically limited by the resolution of the converters in the system. SNR is mathematically defined as the ratio of the carrier signal level to the sum of all noise spectral components (excluding the first five harmonics and DC), where:

SNR = Signal-to-Noise Ratio (dB)

Carrier Signal = RMS value of the carrier signal (peak or full scale)

Spectral Noise = RMS sum of all noise spectral components except the first five harmonics

A noisy power supply can degrade the SNR by coupling in the carrier signal and adding noise spectral components to the output spectrum. As shown in Figure 2, the SNR of the AD9208 high speed ADC is reduced from 56.8 dBFS to 51.7 dBFS when a 1 MHz power supply ripple generates spectral noise components in the FFT output spectrum.

Phase noise is a measure of the frequency stability of a signal. Ideally, an oscillator should be able to produce a specific set of stable frequencies over a certain period of time. But in the real world, there are always some small interfering amplitude and phase fluctuations in the signal. These phase fluctuations or jitter are distributed on both sides of the signal in the frequency spectrum.

Phase noise can be defined in a number of ways. In this article, phase noise is defined as single sideband (SSB) phase noise, a common definition that uses the ratio of the power density of the carrier signal at the offset frequency to the total power of the carrier signal, where:

SSB PN = Single Sideband Phase Noise (dBc/Hz)

Sideband power density = Noise power per 1 Hz bandwidth at the carrier signal offset frequency (W/Hz)

Carrier power = Total carrier power (W)

Figure 2. SNR of the AD9208 high speed ADC using (a) clean supplies and (b) noisy supplies.

Figure 3. (a) Two different supplies with significantly different amounts of output noise. (b) Phase noise performance produced by the ADRV9009 when powered from each of these two supplies.

For analog signal processing devices, voltage noise coupled into the device clock through the clock supply voltage generates phase noise, which in turn affects the frequency stability of the internal local oscillator (LO). This expands the range of LO frequencies in the spectrum, increases the power density at offset frequencies relative to the carrier, and thus increases phase noise.

Figure 3 compares the phase noise performance of the ADRV9009 transceiver when powered from two different supplies. Figure 3a shows the noise spectrum of the two supplies, and Figure 3b shows the resulting phase noise. Both supplies are based on the LTM8063 µModule® regulator using spread spectrum frequency modulation (SSFM) ^. The benefit of SSFM is that it improves the noise performance of the converter’s fundamental switching frequency and its harmonics by spreading the fundamental frequency over a range. This can be seen in Figure 3a—note the relatively broad noise peaks at 1 MHz and its harmonics. The trade-off is that the triangle wave modulation frequency of SSFM will generate noise below 100 kHz—note the peak starts at around 2 kHz.

A low-pass filter is added to the backup supply to suppress noise above 1 MHz, and an ADP1764 low dropout (LDO) post regulator is added to reduce the overall noise floor, especially the noise below 10 kHz (mainly the noise generated by SSFM). Due to the additional filtering, the overall power supply noise is improved, thereby enhancing the phase noise performance below the 10 kHz offset frequency, as shown in Figure 3b.

The sensitivity of a load to power supply ripple can be quantified by two parameters:

• Power Supply Rejection Ratio (PSRR)

• Power Supply Modulation Ratio (PSMR)

PSRR is a measure of the change in output offset caused by changes in the DC supply voltage. This is rarely a concern, as the power system is supposed to provide a stable, regulated DC voltage to the load. On the other hand, AC PSRR is a measure of the ability of the device to reject AC signals in the DC supply over a range of frequencies.

AC PSRR is determined by injecting a sine wave signal at the device’s power supply pins and observing the error spurs that appear on the data converter/transceiver output spectrum noise floor at the injection frequency (Figure 4). AC PSRR is defined as the ratio of the measured injected signal amplitude to the corresponding error spur amplitude on the output spectrum, where:

Error Spur = Amplitude of spurs in the output spectrum caused by injected ripple

Injected Ripple = Amplitude of the sine wave coupled and measured at the input supply pins

Figure 4. Error spurs in the output spectrum of an analog signal processing device caused by power supply ripple.

Figure 5 shows a block diagram of a typical PSRR setup. Taking the AD9213 10 GSPS high speed ADC as an example, a 1 MHz, 13.3 mV peak-to-peak sine wave is actively coupled onto a 1.0 V analog supply rail. The corresponding 1 MHz digitized spur appears above the –108 dBFS FFT spectrum noise floor of the ADC. The 1 MHz digitized spur is –81 dBFS, which corresponds to a peak-to-peak voltage of 124.8 μV referenced to the analog input full-scale range of 1.4 V peak-to-peak. Using Equation 4 to calculate the 1 MHz ac PSRR, we obtain an ac PSRR of 40.5 dB at 1 MHz. Figure 6 shows the ac PSRR of the AD9213 1.0 V AVDD rail.

Figure 5. Simplified block diagram of the PSRR/PSMR test setup.

Figure 6. AD9213 high speed ADC ac PSRR for 1.0 V AVDD rail.

PSMR affects analog signal processing devices differently than PSRR. PSMR represents the sensitivity of a device to power supply noise when modulated with an RF carrier signal. This effect can be seen as modulation spurs around the carrier frequency applied to the device, appearing as carrier sidebands.

Power supply modulation is achieved by combining the input ripple signal with a clean DC voltage using a line injector/coupling circuit. The power supply ripple is injected into the power supply pins as a sine wave signal from a signal generator. The sine wave modulated onto the RF carrier generates sideband spurs with an offset frequency equal to the sine wave frequency. The spur level is affected by the sine wave amplitude and the device sensitivity. The simplified PSMR test setup is the same as that for PSRR, as shown in Figure 5, but the output primarily shows the carrier frequency and its sideband spurs, as shown in Figure 7. PSMR is defined as the ratio of the power supply injected ripple amplitude to the amplitude of the modulation sideband spurs around the carrier, where:

Modulation spurious = the amplitude of the carrier frequency sideband spurious caused by the injected ripple

Injected Ripple = Amplitude of the sine wave coupled and measured at the input supply pins

Figure 7. Modulation sideband spurs in the carrier signal caused by power supply ripple.

Assume that the AD9175 12.6 GSPS high speed DAC is operating at a 100 MHz carrier with a 10 MHz power supply ripple of approximately 3.05 mV peak-to-peak actively coupled onto the 1.0 V AVDD rail. The corresponding 24.6 μV peak-to-peak modulation spur appears in the sidebands of the carrier signal with an offset frequency equal to the power supply ripple frequency of approximately 10 MHz. Using Equation 5 to calculate the PSMR at 10 MHz, we obtain 41.9 dB. Figure 8 shows the AD9175 1.0 V AVDD rail PSMR for channel DAC0 at various carrier frequencies.

Figure 8. AD9175 high speed DAC PSMR for 1.0 V AVDD rail (channel DAC0).

The PSMR can be combined with the reference threshold of the powered device to determine the maximum allowable voltage ripple for each power domain of the analog signal processing device. The reference threshold itself can be one of several values, representing the allowable spurious level (caused by the power supply ripple) that the device can tolerate without significantly affecting its dynamic performance. This spurious level can be a spurious-free dynamic range (SFDR), a percentage of the least significant bit (LSB), or the output spectral noise floor. Equation 6 shows the maximum allowable input ripple (VR_MAX) as a function of the PSMR and the measured noise floor of each device, where:

VR_MAX = Maximum allowed voltage ripple on each supply _rail before spurs appear in the output spectral noise floor

PSMR = Noise sensitivity of target power rail (dB)

Threshold = predefined baseline threshold (output spectrum noise floor in this case)

For example, the output spectral noise floor of the AD9175 is approximately 1 μV p-p. The PSMR of an 1800 MHz carrier with a 10 MHz ripple is approximately 20.9 dB. Using Equation 6, the maximum allowable ripple that can be tolerated in the device's power supply pins without degrading its dynamic performance is 11.1 μV p-p.

Figure 9 shows the combined results of the spectrum output of the LT8650S step-down Silent Switcher® ^regulator (with and without an output LC filter) and the maximum allowed ripple of the AD9175 1.0 V AVDD rail. The regulator spectrum output contains spurs at the fundamental switching frequency and its harmonics. The LT8650S directly powering the AD9175 generates a fundamental frequency that exceeds the maximum allowed threshold, resulting in modulation sideband spurs in the output spectrum, as shown in Figure 10. Simply adding an LC filter can reduce the switching spurs to below the maximum allowed ripple, as shown in Figure 11.

Figure 9. Power spectrum output of the LT8650S on a 1.0 V AVDD rail versus maximum allowed voltage ripple.

Figure 10. Output spectrum of the AD9175 DAC0 at 1800 MHz carrier frequency (directly output to the AVDD rail using an LT8650S DC-DC Silent Switcher converter).

Figure 11. Output spectrum of the AD9175 DAC0 at 1800 MHz carrier frequency (using the LT8650S with LC filter power supply).

The excellent dynamic performance of high-speed analog signal processing devices can be easily weakened by power supply noise. In order to avoid system performance degradation, the sensitivity of the signal chain to power supply noise must be fully understood. This can be determined by setting the maximum allowable ripple, which is critical to the power distribution network (PDN) design. Once the maximum allowable ripple threshold is known, various methods can be used to design an optimized power supply. If the maximum allowable ripple has a good margin, the PDN will not degrade the dynamic performance of the high-speed analog signal processing device.