How much does it cost to design a 2nm chip?
Latest update time：2022-12-15
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Recently, Marvell executives stated at an analysis meeting that with the evolution of manufacturing processes, chip research and development costs are soaring.
As shown in the figure below, at 28nm, the cost of designing a chip was only US$42.8 million. In the next 22 and 16nm, chip design costs will rise steadily, but the extent is still controllable. By 10nm, chip costs have skyrocketed.
As shown in the figure above, by 7nm, the design cost of the chip has reached 249 million US dollars. For comparison, the design cost of the 16nm chip is 89.8 million US dollars. By 5nm, chip design costs have further soared to US$449 million, by 3nm it has reached US$581 million, and by 2nm it will further increase to US$724 million.
In the author's opinion, according to this growth rate, chip design costs will exceed US$1 billion soon.
From this figure shared by Marvell, we can see that software accounts for the majority of chip design costs, followed by Verification, Validation, physical, IP qualification, prototype and architecture. According to the above display, originally at 28nm, software was the biggest cost of chip design, but this situation was reversed at 22nm and 16nm. But after entering 10nm, this situation reappeared. From this we can see the challenges that advanced processes bring to the chip design industry.
Why are advanced process chips so expensive?
According to the manufacturing process of chips, it can be divided into main industrial chain and supporting industrial chain: main industrial chain includes chip design, manufacturing and packaging and testing; supporting industrial chain includes IP, EDA, equipment and materials, etc. Among them, the high cost is mainly composed of manpower and R&D expenses, tape-out expenses, IP and EDA tool licensing fees, etc. At the same time, the cost of fab investment, wafer manufacturing and related equipment involved in the chip manufacturing process will also be allocated to the overall cost of the chip. The more advanced the process is, the higher the cost will be.
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Wafer foundry cost
According to CEST's model, a single 300mm wafer built on the 5nm node costs approximately $16,988, and a similar wafer built on the 7nm node costs $9,346. It can be seen that the foundry price of each wafer is more than US$7,000 higher for the 5nm process node than the 7nm wafer of the same size.
Calculate the foundry sales price of each chip in 2020 by node (Source: CSET)
It can be inferred from this that the cost of wafers built on the 3nm node may reach about US$30,000, and the cost of wafer foundry will further increase.
Another set of data also confirms this. The cost price depends largely on the chip manufacturing process and wafer size. Data provided by IC Insights shows that the difference between the foundry revenue of each 0.5µ 200mm wafer ($370) and the foundry revenue of ≤20nm 300mm wafer ($6050) is more than 16 times. Even under the same 300mm wafer size, the cost difference of ≤20nm is doubled compared to the 28nm process.
Foundry revenue per wafer by major technology nodes and wafer sizes in 2018 (Source: IC Insights)
It can be seen that with the improvement of process nodes, the cost of wafer foundry has increased significantly.
In addition, in addition to the cost of fab construction and foundry, the daily operating investment of wafer manufacturers is also not low (of course, this part has been evenly allocated to the foundry cost).
Data from TSMC's corporate social responsibility report shows that TSMC's global energy consumption reached 14.33 billion kWh in 2019. For comparison, the annual residential electricity consumption in Shenzhen City with a permanent population of 13.4388 million in 2019 was 14.664 billion kWh. This shows how much electricity TSMC consumes in a year.
Moreover, the higher the precision of the process or the higher the precision of the lithography equipment, the power required will increase proportionally. According to Taiwanese media reports, taking 5nm as an example, when TSMC’s 5nm chips are being mass-produced, the company’s power consumption per unit product has increased by 17.9% compared to 2019.
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Mask cost
Mask, also known as photomask, photomask, etc., is a pattern transfer tool or master in the microelectronics manufacturing process. Its function is similar to the "negative" of a traditional camera. According to the graphics required by the customer, the photolithography plate making process , which engraves micron- and nano-level fine patterns on the mask substrate, is a carrier that carries graphic design and process technology.
According to IBS data, in the 16/14nm process, the cost of the mask used is about US$5 million. By the 7nm process, the mask cost quickly rises to US$15 million.
In the 7nm process, the mask cost is approximately US$15 million (Source: IBS)
We also learned from TSMC (IEDM 2019) that from 10nm to 5nm, with the application of EUV lithography technology, the number of masks used has decreased. The number of masks used in the 5nm and 10nm processes is similar.
Number of Masks in different processes (Source: TSMC)
However, while the number of masks is basically the same, more advanced manufacturing processes have increased the total cost of masks, which can reflect the rising average cost of masks.
Reflected on the chip cost, the mask cost of each CPU is equal to the total mask cost/total output. If the overall output is small, the cost of the chip will be higher due to the mask cost; if the output is large enough, such as hundreds of millions of shipments per year, the mask cost will be amortized by the huge output, which can significantly reduce the mask cost of each CPU. , making a CPU with the attributes of "more expensive process technology + larger output" cheaper than a CPU with "cheap process technology + smaller output".
It is foreseeable that by 3nm, mask costs are expected to rise again, further increasing chip costs.
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EUV lithography machine
As one of the core equipment in the chip manufacturing stage, the photolithography machine is responsible for "engraving" circuit patterns. Its accuracy determines the accuracy of the process. The principle is to print the designed chip pattern on the mask, and then use a laser beam to pass through it. The patterned mask and optical lens expose the chip pattern on the silicon wafer with photoresist coating, and finally transfer the pattern on the mask to the chip photoresist coating.
With the development of process technology, when reaching 7nm and more advanced technology nodes, shorter wavelength extreme ultraviolet (EUV) lithography technology is needed to achieve smaller processes. ASML of the Netherlands is the only manufacturer in the world capable of manufacturing EUV lithography machines.
TSMC introduced EUV equipment at 7nm+, but the number of layers was relatively limited; 6nm added EUV layers and optimized the PDK (Process Design Kit); 5nm has full EUV capabilities. As chips move toward 3nm and more advanced processes, chip manufacturers will need a new technology for EUV lithography with high numerical aperture EUV (high-NA EUV). According to ASML's financial report, they are developing a next-generation EUV lithography machine using high-NA technology, which has higher numerical aperture, resolution and coverage capabilities, which will be 70% higher than the current EUV lithography machine.
However, the price of EUV lithography machines has always been very expensive. In 2018, SMIC and ASML signed an ordering agreement and ordered an EUV lithography machine for US$120 million. This price is basically consistent with the EUV lithography machine price disclosed by PHOTRONICS.
Equipment costs (Source: PHOTRONICS)
Judging from ASML's latest financial report for the second quarter of 2021, as of July 4, 2021, ASML has shipped 16 EUV lithography machines this year, with sales reaching 2.4561 billion euros, and the average price of each EUV lithography machine is as high as 1.535 billion euros.
ASML 2021 Q2 financial report (Source: ASML)
Combined with ASML's financial report data over the past three years (2018/2019/2020), we can see that ASML's EUV lithography machine orders have increased from 104.5 million euros to 144 million euros, with prices rising year by year.
ASML’s financial reports for the past three years (Source: ASML)
An EUV lithography machine costs more than 100 million US dollars, and it is quite difficult to buy. Every time ASML launches a new generation of EUV lithography machines, the production capacity of the new equipment is steadily increasing, but the price is naturally higher. According to reports, ASML's second-generation EUV lithography machine will be the NXE:5000 series, which will further improve lithography accuracy. It was originally planned to be released in 2023, but has been postponed to 2025-2026, and the price is expected to exceed US$300 million.
Of course, in addition to the most expensive EUV lithography machine, the equipment and materials used in deposition, etching, cleaning, packaging and other links are also expensive, and the costs are increasing as the process advances.
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R&D & labor costs
Advanced processes not only require huge construction costs, but high R&D and labor costs also raise the threshold for design companies.
Chip design includes circuit design, layout design, mask production, etc., which requires consideration of many factors and knowledge structures. Taking the familiar 5G SoC as an example, industry manufacturers can integrate self-developed independent AI processing unit APU, multi-mode communication baseband, camera ISP, various control switches, micro-core and other self-developed modules. This part of the cost is difficult to estimate specifically and is a long-term R&D achievement, but the intensity of investment can be seen from the labor cost.
Labor costs are an important part of R&D costs. Project development efficiency and quality are related to the number and level of engineers. The annual salary of domestic senior chip design engineers is generally between 500,000 and 1 million yuan. It is understood that when Xilinx was developing a 7nm process FPGA chip code-named Everest, it took 4 years and 1,500 engineers to successfully develop it. The project cost more than $1 billion. This is already the case for FPGA chips, and the investment required for more complex high-end CPU and GPU chips is huge. Nvidia used 2,000 engineers to develop Xavier, and the development cost has reached 2 billion US dollars.
The development cost of a chip depends on the chip size, chip type, etc. Industry insiders say that the most expensive designs (such as some high-end CPUs) are higher than the data provided by IBS, but other designs (such as some ASICs) are higher than the data provided by IBS. The data is much lower. Taken together, as chip design types and forms vary widely and are constantly changing, it is difficult to predict their specific costs.
On the other hand, the shift to GAA in transistor architecture is also increasing chip costs.
Currently, as the aspect ratio continues to increase, FinFET is approaching the physical limit. In order to create higher-density chips, all-around gate transistors (GAAFET) have become a new technology choice. Therefore, the transistor structure moving from FinFET to GAA has become the key to the survival of Moore's Law.
Samsung, TSMC, and Intel have all introduced research on GAA technology. Samsung has taken the lead in using GAA for 3nm chip design. However, GAA currently faces various challenges including n/p imbalance, bottom plate effectiveness, internal spacing, gate length control and device coverage.
In the process of technological change, new technologies require more time to develop, and new technologies and equipment are required in every link, all of which increase the cost of chip development.
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EDA cost
EDA covers all processes such as integrated circuit design, verification and simulation. The chip's purpose, specifications, characteristics, and manufacturing processes are almost all completed at this stage. EDA tools can be used to design extremely complex circuit diagrams to create powerful chips.
According to ESD Alliance data, the global market size of EDA in 2020 is US$11.467 billion, which is relatively small compared to the chip market of several hundred billion US dollars. However, EDA plays a crucial role in the efficiency and cost of chip design.
EDA is an industry with a small market size but a long technical process. It requires a wide variety of software and hardware tools to cooperate with each other to form a tool chain. Taking EDA giant Synopsys as an example, its tool chain that completely covers the entire chip design process claims to have more than 500 tools. kind. Judging from the financial reports of Synopsys and Cadence, revenue in 2020 was US$3.69 and US$2.68 billion respectively. The two companies' annual investment in R&D reached more than 35%, and Synopsys' R&D expenses reached an astonishing US$1 billion level. The R&D costs of EDA software are increasing at an accelerated pace.
Synopsys 2021 Q2 financial report (Source: Synopsys)
According to Synopsys' latest financial report, revenue in the second quarter of 2021 was US$1.0243 billion, semiconductor and system design, including EDA tools, IP products, system integration solutions and related services; software integrity, including security and quality solutions etc. EDA revenue reached US$587.6 million, accounting for about 57%.
Synopsys financial report data (Source: Synopsys)
According to online data, the purchase cost of EDA tools required for a 20-person R&D team to design a chip is US$1 million per year (including the purchase cost of IP such as EDA and LPDDR). It can be predicted from the industry attributes of EDA and high R&D investment that when the 3nm process is reached, the EDA tool licensing fee will naturally be even more expensive.
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IP licensing cost
Semiconductor IP refers to those design modules in integrated circuit design that have been verified, reusable, have certain certain functions and independent intellectual property rights. Chip companies can achieve a specific function by purchasing IP (such as ARM's Cortex series CPU, Mali series GPU IP authorization, etc., other small modules also need to be purchased, such as audio and video codecs, DSP, NPU, etc.). This development model similar to "building blocks" can greatly shorten the development cycle of the chip. Reduce the difficulty of chip design while improving performance and reliability.
Chip design is mainly due to the fact that the underlying architecture of the chip core (intellectual property rights and technical barriers) is in the hands of a few manufacturers, and patent fees may reach more than 50% of the design cost. It is understood that ARM in the past usually required customers to choose a specific chip design and pay a licensing fee in advance. This model generally requires manufacturers to spend millions of dollars at a time to be allowed to use it (the specific amount depends on the complexity of the licensed technology, usually between US$1 million and US$10 million). At the same time, after the chip is put into production, it will be A royalty of 1%-3% of the final selling price of the chip is paid to the IP manufacturer.
On the other hand, according to Synopsys and Cadence performance data, Synopsys's IP and system integration revenue proportion increased from 28% in 2017 to 33% in 2020, reaching US$12.026 million; Cadence's IP revenue proportion increased from 28% in 2016 to 33% in 2020. from 11% in 2020 to 14% in 2020.
Synopsys revenue breakdown from 2017 to 2020 (unit: million US dollars)
It can be seen that IP is the value node with the highest technical content. As chip manufacturing processes become more and more advanced and chip prices increase, the difficulty of IP research and development and licensing fees will also increase.
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