2017 Silicon Process RF Microwave Integrated Circuit System Seminar and the 52nd International Lecture

(1) WeChat registration: Follow the WeChat public account “National IC Talent Training Platform” (WeChat ID: ICPlatform), click the tab “Online Registration - October Event Registration” below, and fill in the relevant information.

(2) Email registration:

Registration receipt download link:

http://www.icplatform.cn/form

(Send registration information to icplatform@miitec.cn;

Email subject format: " Registration + 2017 Silicon Process RF Microwave Integrated Circuit System Seminar + Company Name + Number of People "

Email content: Contains name, unit, department and position, phone number and email address.

(3) Telephone registration: Zhou Jingmei 025-69640097

Zhang Huan 025-69678210

18262610717

1. Time: October 30, 2017 - November 1, 2017 (3 days)

2. Lecture topic: High-performance analog mixed-signal IC design - from low power to high precision to high speed

3. Location: Nanjing Suning Venice Hotel

(No. 198-1, Jingxin, Jiangshan Road, Pukou District, next to Liuzhou East Road Station of Metro Line 3)

resume:

1. Xicheng Jiang received his bachelor's degree from the University of Science and Technology of China, and then studied in the Department of Electrical Engineering at the University of California, Los Angeles, where he received his master's and doctoral degrees.

2. From 1997 to present, he has worked in the analog and RF microelectronics team of Broadcom, and is currently the technical director and "Broadcom Outstanding Engineer" of Broadcom.

3. IEEE Fellow, has served as a technical committee member/subcommittee chairman of ISSCC and CICC for a long time, and has served as the deputy editor-in-chief of IEEE Circuits and Systems Letters.

field of study:

1. Research includes data converters, high-speed serial transceivers, cellular baseband, Hi-Fi audio drivers, microphone interfaces, and precision sensor interfaces.

Honors:

1. He holds more than 40 granted and pending U.S. patents, has authored and co-authored more than 40 conference and journal papers, and his books Digitally-Assisted Analog and Analog-Assisted Digital IC Design were published by Cambridge University Press.

2. Co-recipient of the CICC 2009 Best Paper Award and the CICC 2013 Best Posted Paper Award.

Day 1: Low-power & Precision Circuit Designs

Day 1: Low Power and Precision Circuit Design

Introduction

• Process scaling and device modeling

• Analog Mixed-Signal designs using FinFET

• Analog Mixed-Signal designs using SOI

• Nano-power circuit design techniques

• Analog Techniques for Nano Power Designs

• Practical Low-power Design Examples

• Biasing

• Reference

• Oscillator

• Comparator

• Amplifier

• Case Study

• A 32nW Bandgap Reference Voltage Operational from 0.5V Supply for Ultra-Low Power Systems

• Amplifier classes from Class-A, Class-B, Class-D, Class-G, Class-H

• Precision Class-D amplifiers

• Class-D modulation schemes

• Class-D amplifier architectures

• Practical design examples

• Digital implementation

• Analog implementation

• EMI reduction

• Pop-click suppression

• Emerging trends

• References

• Precision audio CODEC

• Introduction

• Stereo audio CODEC architecture & design

• Audio input path

• Audio output path

• Microphone bias generation

• Measurement results

• Conclusion

Day 2: High-speed SERDES

Day 2: High-Speed ​​SERDES

• The basic of high-speed SERDES

• General SERDES system

• The challenges and solutions

• Equalization techniques for high-speed SERDES

• The channel

• Pre-emphasis

• Analog equalizer

• Linear equalizer

• DFE

• Digital equalizer

• FFE

• DFE

• MLSE

• PAM4

• A practical design example

• The trend of high-speed SERDES designs

• Clock and Data Recovery (CDR) architecture and circuit implementation

• Performance metrics

• Basic architectures

• Linear/Bang-bang

• Digital

• Hybrid

• Application-specific CDRs

• Multi-lane chip-to-chip links

• Repeaters for optical links and active cables

• High-speed SERDES receiver practical design considerations

• BER

• CTLE

• DFE

• RX signal chain

• RX circuit implementations

• Comparator design

• Pre-amplifier design

• CTLE circuit design

• VGA circuit design

• DFE implementations

Day 3: High-speed data converter

Day 3: High-Speed ​​Data Converters

• High-speed ADC architecture

• System level

• Budgeting of non-idealities

• Architecture level

• Time interleaving

• Calibration

• Flash ADCs

• High-speed SAR ADC design

• SAR ADC Architecture

• Circuit Design Considerations

• Advanced SARADC Examples

• Summary

• Voltage reference design

• Bandgap Reference

• Start-up consideration

• Bandgap Trimming

• High-speed DAC design

• Design considerations

• Layout consideration

• Measurement methodology

Registration fee: 5380 yuan/person

Core Power Partner: 5080 yuan/person

On-campus students: RMB 3,580 /person (the department/college where the student is enrolled must provide a proof of enrollment).

Note: The above fees include face-to-face teaching fees, venue fees, materials fees, and lunch fees; students are required to pay for their own transportation, food and accommodation fees , etc.

Guoxin IMEC (Beijing) Information Technology Co., Ltd. was jointly established by the Center and IMEC to provide conference services and issue invoices for this International Lecture Series. The invoices are for training fees. Please remit the registration fee to the following account before October 25, 2017, and indicate the payment information in the remittance notes (No. 52 + unit + participant name).

Application Deadline: October 25, 2017

ways of registration:

1. Email registration (recommended)

Registration receipt download link:

http://www.icplatform.cn/form

Fill in the registration receipt form and send the electronic version of the Word form to the "National IC Talent Training Platform" mailbox.

Email address: icplatform@miitec.cn,

The format of the receipt form file name and email title is:

“ Registration + 52nd issue + unit name + number of people ”.

2. Register via WeChat

Follow the WeChat public account "National IC Talent Training Platform" (WeChat ID: ICPlatform), and click the tab "Online Registration-October Event Registration" below to fill in the relevant information.

Note: Registration is considered successful only after submitting the application form and paying the application fee

3. Preferential policies

(1) Core Power partners enjoy preferential prices. For details, please contact Mr. He from the Industry Cooperation Group at 010-68208714.

(2) Bonus Class I, II, and III preferential policies are introduced for colleges and universities:

For details, please edit " class " and send it to the WeChat public account "National IC Talent Training Platform".

The conference affairs team booked a hotel for the students. The information is as follows:

Hotel Name: Nanjing Suning Venice Hotel

Hotel address: No. 198-1, Jingxin, Jiangshan Road, Pukou District, next to Liuzhou East Road Station of Metro Line 3

Negotiated price:

Standard double room (including breakfast) 368 yuan/room

Standard King Room (including breakfast for two) 368 yuan/room

Reservation method: Students who need to book a hotel please fill in the following information and send an email to icqy@miitec.cn according to the example below before 17:00 on October 25th .

Reservation email subject format: "Issue 52 + Hotel Reservation"

Reservation email content: "Name + Gender + Room Type + Check-in Time + Check-out Time + Mobile Number + Whether to Share a Room"

Note:

(1) Within two working days after the hotel reservation is successfully made , the conference affairs team will send you a confirmation email.

(2) To facilitate students' accommodation and lectures and to improve the service level, this International Master Lecture Hall provides a contracted hotel reservation service. After the reservation is successful, we will prepay the deposit on your behalf, and the room cannot be cancelled.

Hotel reservation contact:

Zhang Huan 18262610717 ; 025-69678210

zhanghuan@miitec.cn