NI invites you to SEMICON to explore power semiconductor testing
The power semiconductor track is hot, especially in the electric vehicle and energy industries. So, how to ensure the performance of power semiconductors? The key is accurate testing. NI will demonstrate its latest power semiconductor testing solutions at SEMICON ( NI booth number: Hall N4 N4356 ), and you can also communicate with SET technical engineers on site.
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For H3TRB dynamic testing, SET provides a system that translates the industry’s expanded requirements into automated dynamic testing. The system pays special attention to flexibility so that it can quickly meet changing requirements.
Dynamic H3TRB/DRB test system
◆Each system has 80-240 devices under test (80 devices under test and 1 high-voltage power supply)
◆0V to 1500V; 4A, for 80DUT
◆Single DUT leakage current measurement (during static H3TRB)
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80 measurement channels
◆Provide single DUT overcurrent protection by turning off the switch
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Hardware-based fast shutdown of a single DUT with 65mA±20% during stress phase and 650μA±20 during readout phase
◆Single DUT voltage control
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Active voltage control compensates load voltage to <±0.5V
◆Maximum output voltage up to 1500V
◆Output frequency is configurable from 0Hz to 500kHz (maximum frequency depends on voltage and DUT capacitance)
◆The duty cycle is variable between 25% and 75%, with one gear every 5%
◆Fully automatic test program
◆Measurement data is saved in tdms file
◆Software based on NILabVIEW and TestStand
◆Use software to connect and evaluate the external safety lock of the test chamber
◆Safe voltage monitoring of high-voltage plug connections
◆Safe release of high-voltage power supply equipment
The latest generation of power semiconductor SiC has successfully met the demand for high-power and high-energy-efficiency applications by virtue of its advantages in bandgap width and thermal conductivity. What are the challenges and solutions to SiC testing? The following technical article describes the implications of using the Dynamic Gate Stress (DGS) test process for new reliability testing of SiC-based power semiconductors . I believe you will be inspired after reading it.
Silicon carbide (SiC) components offer numerous technical advantages for demanding applications. However, there are structural differences between silicon (Si) components and SiC components, which will affect reliability testing.
SiC (silicon carbide) has become an important material in the semiconductor market due to its many excellent properties. SiC has a higher electrical breakdown voltage than silicon, thus improving component performance and efficiency. SiC also supports operation at higher temperatures, which is more conducive to heat dissipation and allows for better performance in a smaller space. Because SiC has high thermal conductivity, components can operate efficiently under harsh conditions. The high switching frequency of SiC components enables smaller and lighter designs, which is a major advantage allowing them to be used in numerous applications. Thanks to the above characteristics, SiC is involved in an increasingly wide range of application industries, such as electric vehicles, renewable energy, industrial drive technology and aerospace.
Despite the broad application prospects of SiC, specific reliability tests need to be developed for new SiC-based components. Due to structural differences between SiC and silicon, existing silicon component testing methods and assumptions cannot be used. SiC has a different crystal structure than silicon and therefore has different electrical and thermal properties. If these differences are ignored, potential lifecycle or performance weaknesses of the component may not be detected.
This article introduces the significance of new reliability testing of SiC-based power semiconductors using the Dynamic Gate Stress (DGS) test process.
DGS testing is mainly used for
SiC-FET (Field Effect Transistor)
. During the test, a stress signal is applied to the gate of the DUT (device under test) in the form of a square wave signal that uses the maximum and minimum gate voltage of the DUT. During stress cycling, active temperature control is used to adjust the DUT to the desired stress temperature. The stress application is paused at specified intervals to measure the DUT's gate threshold voltage and RDSon.
For wide bandgap semiconductor testing processes, there are significant differences between dynamic stress methods and static stress methods. The test process described in this article uses the test system of SET GmbH. Use this test set to accurately interpret test specifications and compare measurement results with real-world applications. Correct measurement procedures are equally important to obtain reliable and repeatable measurement results. For testing related content, please refer to ECPE (European Center for Power Electronics) Guideline AQG 324, which provides practical specifications and guidance for the new testing process of SiC components in Europe.
Dynamic Gate Stress (DGS) Testing: Functional Principle and Measurement Procedure
During DGS testing, the FET connects its drain and source contacts to ground potential and applies stress to its gate contact (Figure 1). The applied stress signal is defined in the AQG324 guide. The stress signal parameters are as follows: The amplitude of the square wave signal is the maximum negative and positive voltage allowed by the required DUT specifications. The rise time (dV/dt) of the DUT should be around 1V/ns, the stress frequency should be greater than or equal to 50 kHz, and the duty cycle should range from 20% to 80%.
Figure 1: Test setup for DGS testing: stress circuit on the left and measurement circuit on the right.
The duration of stress is determined by frequency, so the higher the frequency, the shorter the test time. According to guideline AQG324, the stress duration should be no less than 10^11 cycles. The test temperature should be actively adjusted and strictly controlled at 25 °C.
As part of this test process, gate threshold voltage and RDSon resistance are measured during a fully automated stress pause. Accurate measurement and proper pre-processing are very important during testing. Preprocessing is used to ensure that the conditions of the test object are the same for each measurement, thus ensuring that the measurement results are comparable. The AQG guideline in this article references JEDEC guideline JEP184, which describes proper measurement procedures. The gate definition voltage should correspond to the recommended effective gate-source voltage or the maximum/minimum allowed gate-source voltage.
A common preprocessing time is 100ms, but sometimes it can be significantly longer. After the preprocessing is completed, the gate threshold voltage should be measured quickly, and according to the guidelines, the measurement should be performed within 10ms. The oscilloscope recording results shown here were made by SETGmbH's DGS system and are used to illustrate the measurement process.
The curve in Figure 2 corresponds to the gate signal. At the beginning, a stress application phase of -10V~+22V at 300kHz can be observed, followed by a pause at the beginning of the measurement process.
The measurement process starts with a +22V preconditioning pulse lasting 100ms. The gate voltage then changes continuously in very small steps. During the test phase, the drain current Idrain is measured and set to a specific value, say 20mA. Since the FET is turned on, 20mA is flowing at the beginning of the "Vth(down)" test phase. Once the gate voltage approaches the threshold voltage, the FET slowly turns off and the current that was previously fully available through the FET slowly decreases. When the Idrain current reaches a defined value (e.g. 10mA), the gate voltage is saved as Vth(down). Repeat the same measurement procedure for the negative voltage region: minimum gate voltage -10V for 100ms. The gate voltage then gradually increases, holding the Vth(up) voltage at 10mA.
Figure 2: Gate signal of the DGS system during measurement.
After the Vth measurement is completed, measure the Rds(on) resistance of the test object. For this purpose, an adjustable current pulse is generated between the drain and source. Determine the Rds(on) resistance by measuring the voltage drop between drain and source. After completing these measurements, proceed with dynamic gate stress testing. Reliable implementation of this process is crucial to accurately characterize the behavior of SiC semiconductors under stress and guarantee their reliability.
Comparison of DGS measurement results and static measurement results
In order to evaluate the necessity of DGS testing and compare it with the traditional static testing process, a large number of comparative experiments were carried out. A conventional 1200V SiC MOSFET with an RDSon of 80mΩ was used as the test object. The MOSFETs used in this process are of the latest generation and are currently available on the open market. Use the maximum recommended gate voltage from the datasheet at 100kHz stress frequency and 50% duty cycle as the stress parameter for the following tests. The entire testing process was conducted under stable laboratory conditions of 25 °C.
Analysis of the resulting data showed that there are significant differences between static and dynamic testing processes (Figure 3).
Figure 3: Comparison of dynamic and static gate stress measurements.
According to the graph, it can be seen that there is a significant difference between the two, especially in terms of gate threshold voltage drift. During the dynamic test, after 300 gigabit cycles, the gate threshold voltage showed an obvious drift greater than 4V. This drift effect was not observed in static tests. A standard MOSFET has a drift of about 0.5 V, while the drift in dynamic testing was 7 times higher than normal. For most circuits, this increase in voltage can cause significant performance degradation or even circuit failure. SET GmbH repeatedly identified these deviations in dynamic tests; however, no such drifts were found in static tests.
In addition, the relationship between changes in gate threshold voltage and RDSon resistance was further studied. Figure 4 clearly illustrates the relationship between threshold voltage drift and RDSon resistance, based on the measurement results of the first test in Figure 3. It can be assumed that when the gate threshold voltage drifts, the RDSon resistance will also change according to the component's characteristic data curve. This relationship affects component efficiency during operation and, therefore, has implications for practical applications such as electric vehicle range. The specific effects of operating conditions are estimated based on continuous measurements during testing.
Figure 4: Correlation between DUT’s threshold voltage and Rds(on) resistance.
In order to continuously improve the understanding of SiC power semiconductor phenomena, further development of DGS testing and all other dynamic testing processes should continue. Especially for modeling of long-term analyses, as much data as possible should be collected in order to develop reliable power semiconductors to meet future challenges.
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