Today I will teach you how to stabilize voltage with the correct "posture"~
Bypass capacitors are often required during the development of electronic products. Figure 1 shows a switching regulator that generates a low voltage from a high voltage. In this type of circuit, the bypass capacitor (C BYP ) is particularly important. It must support the switching current in the input path so that the supply voltage is stable enough to support the operation of the device.
Figure 1. The ADP2441 switching regulator with bypass capacitor C BYP on the input .
Because the input capacitor in the buck converter is part of the critical path (hot loop) of this topology, the connection to C BYP must ensure the least possible parasitic inductance. Therefore, the mounting position of this component is crucial. The left side of Figure 2 shows a poor layout. The traces connected to the bypass capacitor are thin. The current flowing into the voltage converter does not flow directly from the bypass capacitor. The bypass capacitor only slightly touches the main circuit. This increases the parasitic inductance caused by the capacitor and reduces the effectiveness of this component. The layout shown on the right side of Figure 2 is recommended. The bypass capacitor is very efficient. The connection itself only causes a very small amount of parasitic inductance. It can also be seen from the figure that the pinout of the converter (for example, a switching regulator) has an impact on the layout of the board. As can be seen on the right side of Figure 2, the distance between the V IN and GND pins is very close, closer than in the poor layout on the left. This way, the loop area between the bypass capacitor and the integrated circuit is smaller.
Figure 2. An unfavorably connected bypass capacitor (left) and a favorable connected bypass capacitor (right).
Since the bypass capacitors should be connected with as little parasitic inductance as possible, it is recommended to place the bypass capacitors and the switching regulator on the same side of the board. However, in some applications, the switching regulator on the top side can only be decoupled from the bypass capacitors on the bottom side of the board. This is the case when there is not enough space for a larger decoupling capacitor. In this case, vias are used to connect the capacitors. Unfortunately, vias generate a parasitic inductance of several nanohenries. In order to achieve the lowest impedance for this connection, various connection recommendations have been proposed, as shown in Figure 3.
Figure 3. When bypass capacitors are connected to vias, there are multiple connection options.
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Version A is not very favorable. In this option, thin traces are used between the vias and the bypass capacitors. Depending on where the support traces run on the other side of the board, this layout arrangement may also result in increased parasitic inductance.
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In version B , the via is located closer to the bypass capacitor, so this connection is more favorable. In addition, two vias are used in parallel. This reduces the total inductance of the entire connection.
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Version C is more advantageous, where the connected loop area is very small, so only a very small amount of parasitic inductance is generated. However, because the bypass capacitor is very small and the manufacturing process is very low cost, it is impossible or impossible to make a via under the component.
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Version D offers a very interesting connection. Depending on how the particular ceramic bypass capacitor is designed, connecting it sideways to the board may provide the least parasitic inductance.
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