Lattice Avant Platform: Tailored for the mid-range FPGA market

For decades, FPGA products have been electronic hardware known and frequently used by design engineers. FPGAs typically use logic cells (LCs) to differentiate logic density. The FPGA market can be divided into three categories based on the number of logic units: high-end, mid-range, and small FPGAs. Although these descriptions will change over time, today's high-end FPGAs generally have more than 500K logic cells, mid-range 100K to 500K, and small FPGAs less than 100K.

From an architectural perspective, it is surprising that many FPGA vendors have not considered the mid-range FPGA space as a strategic priority for a long time. Mid-range FPGAs have become the best choice for various embedded, industrial, automation, and robotics applications. It can be said that there has not been a true mid-range FPGA on the market for nearly a decade.

Vendors, realizing the market need for mid-range FPGAs, often use "waterfall" development to deliver these products. Basically, the architecture optimized for high-end FPGAs is applied to mid-range FPGAs. Although these products can indeed fill the gap in mid-range products, they are not specifically optimized for mid-range FPGAs. Because these architectures are supposed to support up to 10 times the logic density. This strategy may be good for FPGA vendors, but for mid-range FPGA customers, it's a different story.

What customers really want is a mid-range FPGA designed for the mid-range market, not some tweaks to the high-end or small FPGA architecture. The Lattice Avant™ platform is designed for mid-range FPGAs. Compared to existing FPGAs in the mid-range FPGA market, the Avant platform offers the following advantages:

• Power consumption is much lower than similar competing devices

• Package size is much smaller than similar competing devices

• The need for higher DSP performance and support for the latest AI algorithms

• 25 Gbps CORE

• Supports DDR3L/DDR4/LPDDR4 and DDR5

• Next generation security features

• higher reliability

Lattice Semiconductor has long focused on low-power FPGAs and serves the low-density FPGA market. In fact, Lattice ships more than all other traditional FPGA vendors combined. Now the company is strongly entering the mid-range FPGA market with the Avant platform. Through the Avant platform, designers can not only obtain the low power consumption, density optimization and other features provided by Lattice as always, but also obtain higher device density and performance. The result is a family of devices that offer more high-end features but with the size and low power consumption of mid-range (and small) devices.

The potential applications of the Avant FPGA platform are vast. In the industrial field, it can be used in network controllers, PLCs, network edge computing, machine vision and industrial robots. Thanks to its powerful DSP performance, it is also valuable in the fields of automotive networking and software-defined radio. In addition, general wireless communications, indoor 5G small base stations and 5G fronthaul applications are also potential application areas for Avant.

Avant implements a range of high-bandwidth I/O standards such as PCIe® Gen4, LPDDR4 and DDR5, and provides powerful DSP and load acceleration performance. The Avant FPGA fabric supports clock rates up to 350 MHz, and the embedded RAM blocks and DSP multiply/accumulate blocks support clock rates up to 625 MHz. These devices are the industry's smallest FPGAs offering 25 Gbps SERDES functionality.

Security should be a primary consideration in all embedded designs. To this end, Lattice engineers ensured that the Avant platform included security features such as AES256-GCM, ECC, RSA, tamper resistance and Physical Unclonable Function (PUF). These features encrypt and authenticate configuration and user data, ensuring that the FPGA remains secure even from malicious attacks. Soft failure detection and correction quickly detects environmental factors that cause soft failures so that appropriate actions can be taken.

Authentication and encryption protect the FPGA's configuration bitstream. User-mode security functions are implemented through hard-core cryptographic engines, which are available as embedded IP blocks in the FPGA fabric. Tamper resistance against side channel and fault injection attacks is achieved by zeroing out keys and sensitive data.

In addition to strong safety features, Avant devices are resistant to transient soft failure failures caused by alpha particles. The detection and recovery of single-event upsets need to be performed quickly to ensure normal operation of the system and enhance reliability.

One strategy the Avant platform uses to reduce power consumption is to implement the logic using a four-input LUT instead of a six-input LUT. A four-input LUT requires only 16 SRAM configuration bits to program the LUT, while a six-input LUT requires 64 SRAM configuration bits.

Another aspect of power optimization is reducing high capacitance networks. Higher fanout networks create greater capacitance through high drive strength buffers connected to high capacitance metal routing. The Avant architecture utilizes small multiplexers and low fan-out networks to reduce power consumption. It is also worth noting that Avant devices are manufactured using a 16nm FinFET process, which is optimized to greatly reduce leakage current.

Sufficient DSP blocks are critical for various signal processing and AI functions in mid-range FPGAs. Avant devices offer up to 1800 18 x 18 multipliers capable of fully pipelined operation at 625 MHz. This DSP block can also function as three 9 x 9 or four 8 x 8 multipliers with a built-in 18-bit pre-adder and 48-bit accumulator. These configuration modes are significantly superior to traditional devices. Additionally, the multipliers can be cascaded into 27 x 18, 36 x 18, 27 x 27, or 36 x 36 configurations.

I/O flexibility is a cornerstone of the Avant architecture. FPGA provides SERDES and parallel I/O standards to meet the needs of various applications. As far as the SERDES standard is concerned, it includes PCIe Gen 4, 25G Ethernet, DP/eDP, SLVS-EC, CoaXPress, JESD204B/C, eCPRI/CPRI, RoE and SyncE. In addition, to speed up PCIe implementation, a hard-core PCIe controller is also provided. GPIO supports multiple interfaces including LVCMOS 0.9-3.3V, 1.8 Gbps MIPI D-PHY, 1.6 Gbps LVDS/subLVDS, I3C, SGMII and LVDS 7:1.

The internal embedded memory uses 36 kbit memory blocks and supports single port, pseudo dual port (1R1W), true dual port (2RW) and ROM configurations. The Lattice Radiant® software memory compiler can assemble and place/route internal memory blocks up to 64 kbit × 256 bits (16 Mbit total). The memory provides a maximum capacity of 36 Mbit.

External memory interfaces include DDR4, DDR5, and LPDDR4 (running at up to 2.4 Gbit/s) as well as legacy standards DDR3L (1.866 Gbit/s) and LPDDR2 (1.066 Gbit/s). These implementations are based on a hard MEMPHY with a flexible soft controller. The soft memory controller supports error correction code (ECC).

From a packaging perspective, the Lattice design team's goal was to provide smaller chips in lower-cost packages, and they did so. This goal is achieved by lower power requirements, resulting in the use of smaller die and lower cost packages, with chip sizes as small as 11x9 mm for 200K logic cells and 15x13 mm for 500K logic cells. .

Lattice Radiant and Lattice Propel™ tools are powerful and intuitive to use, allowing users to efficiently develop FPGA applications using convenient design wizards and accurate implementation. This includes compiler optimization and analysis to achieve fast and predictable design closure. This goal can be achieved through a unified design database, design constraint process, and full-process timing analysis.

Avant provides a complete set of IP to support the platform. Some are hard core (custom logic) configurations to optimize area and performance, while others are provided in soft core form (by using logic cells) for maximum flexibility. PCIe is an example of hard core IP, while external memory interfaces are partially hardened using MEMPHY and soft controllers. In addition, if the soft core is not used, it will not take up any space.

The Avant platform was designed to serve the mid-range FPGA market. Lattice's investment in this area has enabled the platform to have leading power, small size and high performance. The platform's modern feature set supports interconnection using the latest interface standards, further enhancing its leading position. Currently, Lattice Radiant and Propel design tools already support the Avant platform, allowing Lattice customers to quickly apply existing software knowledge. Various IP and development boards also support the platform. For more information, please visit the Lattice Avant website page.