Want to uncover the true nature of phase deviation? Here are some tips from experience

This article identifies several concerns in the design process, manufacturing process, and application environment that may cause phase deviation of 1ps or more. For these concerns, this article will provide some suggestions, examples, and rules of thumb to help readers intuitively understand the root causes and magnitude of phase deviation.

The equations listed here are used to estimate the propagation delay (τ _pd ) of a single clock path and the variation in propagation delay due to multiple clock propagation paths or changes in environmental conditions. In large clock tree applications, ∆τ _pd between clock traces is a component of the total system clock skew. Equations 1 and 2 provide the two main variables that control the τ _pd of a transmission line : the physical length of the transmission line (ℓ) and the effective dielectric constant (Ɛ _eff ). For Equation 1, v _p represents the transmission line phase velocity, V _F represents the velocity factor (%), and c represents the speed of light (299,792,458 m/s).

_{Equation 3 calculates the incremental propagation delay (∆τ pd} ) between two transmission lines .

Transmission line dielectric materials have properties that vary with temperature. The temperature coefficient (TCDk) is usually expressed as a plot of phase change (Δϕ _ppm ) versus temperature in parts per million (ppm); where Δϕ _ppm is the difference between the phase at the target temperature and the phase at a reference temperature (usually 25°C). Equation 4 is used to estimate the change in propagation delay relative to the reference temperature when the temperature, Δϕ _{ppm , and transmission line length are known.}

Coaxial cable dielectric materials have properties that change when the cable is bent. The radius and angle of the cable bend determine the change in effective dielectric constant. This is typically expressed as a change in phase (Δϕ _deg ) by comparing the phase of a particular cable bend to that of a straight cable. For a known Δϕ _deg , signal frequency (f), and cable bend, Equation 5 can be used to estimate the change in propagation delay.

Recommendation : To achieve the best delay matching between multiple traces, match trace lengths and transmission line types.

Rule of thumb :

A 1mm difference between the lengths of two traces is equivalent to ∆τ _pd ~6ps (a 6mil difference between the lengths of is equivalent to ∆τ _pd ~1ps).

Stripline is about 1 ps/mm slower than microstrip or conductor-backed coplanar waveguide (CB-CPW).

Different transmission line types produce different Ɛ _eff and v _p . Using Equation 2, this means that different transmission types of the same physical length will have different τ _pd . Table 1 and Figure 1 provide simulation results for three common transmission lines (CB-CPW, microstrip, and stripline), highlighting the differences between Ɛ _eff , v _p , and τ _pd . The simulation estimates that for a 10 cm CB-CPW trace, τ _pd is 100 ps greater than a stripline trace of the same length. The simulation was generated using the Microwave Impedance Calculator from Rogers Corporation.

Figure 1. Matched transmission line types.

Table 1. Rogers 4003C simulation results for Figure 1

The relative magnetic permeability (Ɛ _r ), also known as the dielectric constant (Dk), of Rogers 4003C is 3.55.

Note that in Table 1, the Ɛ _eff for CB-CPW and microstrip lines is lower because they are exposed to air , where Ɛ _r = 1.

It is not always possible to route signals that require delay matching on the same layer or using the same type of transmission line . Table 2 provides some general factors to consider when selecting transmission line types for different routing. If you need to match τ _pd between different transmission line types , it is best to use a board simulation tool rather than manual calculations and rules of thumb.

Table 2. Generalized Transmission Line Considerations

Tip : If the signal path has vias, remember to consider .

For a rough calculation of propagation delay, assume that the via length connecting two signal layers is the same as the transmission line in phase velocity. For example, a via connecting the top and bottom signal layers of a 62mil thick board will account for an additional τ _pd ~10ps.

建议 ：在走线之间保持最少一个线宽度，避免在Ɛ _eff 出现显著变化。

Rule of thumb :

100Ω differential signaling (odd mode) is faster than 50Ω single-ended signaling.

Closely spaced in-phase 50Ω single-ended signals (even mode) are slower than a single 50Ω single-ended signal.

The signal direction of closely adjacent traces changes Ɛ _eff and, therefore, the delay match between traces of equal length. A simulation of two edge-coupled microstrip traces versus a single microstrip trace is provided in Figure 2 and Table 3. The simulation estimates that the τ _pd of two 10 cm edge-coupled even-mode traces is 16 ps greater than that of an independent single trace of equal length.

Figure 2. Adjacent traces and isolated traces

Table 3. Adjacent and isolated traces

When trying to match a single-ended τ _pd to a differential τ _pd , it is important to emulate the phase . In clocking applications, this can occur when trying to send a CMOS sync or SYSREF request signal that is time-aligned to a differential reference or clock signal. Increasing the spacing between the differential signal paths produces a closer phase speed match between the differential and single-ended signals. However, this comes at the expense of common-mode noise rejection of the differential signal, which serves to keep clock jitter to a minimum.

It is also important to point out that closely spaced in-phase signals (even mode) increase Ɛeff _, which results in a longer τpd _. This occurs when multiple copies of a single-ended signal are closely spaced.

Recommendation : To minimize frequency-dependent delay matching errors, select low Dk, low dissipation factor (DF) materials (Dk < 3.7, DF < 0.005). DF is also known as loss tangent (tan δ) (see Equation 6). For multi-GHz traces, avoid using nickel-containing plating techniques .

Matching the delay between signals at different frequencies to the ps level by canceling out the variation is not an easy task . Figure 3 shows that the dielectric constant generally decreases as frequency increases. Based on Equations 1 and 2 above, this behavior produces a smaller τ _{pd as frequency increases. Based on Equation 3 and the Roger material in Figure 3, ∆τ pd} between a 1GHz and 20GHz sine wave on a 10cm trace is about 4ps.

Figure 3. Dk and DF vs. frequency.

Figure 3 also shows that signal attenuation increases with frequency, resulting in greater attenuation of the square wave’s higher-order harmonics compared to the fundamental tone. The degree of this filtering results in different rise times (τ _R ) and fall times (τ _F ). Changes in rise and fall times manifest themselves as changes in the waveform that affect subsequent receiving devices, which in turn manifest themselves in the total delay parameter, which is composed of the trace’s τ _pd and the signal’s τ _R/2 or τ _F/2 . In addition, square waves of different frequencies may also have different group delays. For these reasons, square waves are more challenging than sine waves when estimating delay matching between different frequencies.

To better understand the relationship between attenuation (α in dB/ft) and frequency, refer Equation 7 and Equation 8 and the references provided in this article 2,3,4,5, which introduce loss tangent (δ) and skin effect. A key point in these references is that skin effect reduces the area (A) in Equation 8, which increases the line resistance (R). 3 To avoid excessive attenuation caused by skin effect at high frequencies, avoid nickel plating techniques such as solder mask over gold (SMOG) plating and electroless nickel immersion gold (ENIG) plating. 4,5 An example of a plating technique that avoids nickel is solder mask over bare copper (SMOBC). In summary, choose low Dk/DF materials, avoid plating techniques that use nickel, and perform board-level delay simulations on critical traces to improve delay matching at different frequencies.

Recommendation : Choose temperature-stable dielectric materials for PCBs and cables. Temperature-stable dielectric materials usually have a Δϕ _{ppm of less than 50ppm.}

The dielectric constant changes with temperature, resulting in a change in the transmission line τ _{pd . Equation 4 calculates the change in delay ∆τ pd} due to the change in dielectric constant caused by temperature change .

Generally, PCB materials fall into two categories: woven glass (WG) and non-woven glass. Since glass has a Dk of 6, fiberglass is usually cheaper and has a higher Dk. Figure 4 compares the Dk variation of various materials. Figure 4 shows that some PTFE/WG-based materials have a steeper TCDk between 10°C and 25°C.

_{Using Equation 3 and Figure 4, Table 4 calculates ∆τ pd} for a 10 cm stripline trace on different PCB materials as the temperature varies from 25°C to 0°C . In a system where τ _pd needs to be matched across multiple traces at different temperatures , the choice of PCB material can result in a τ _pd mismatch of several picoseconds between 10 cm traces .

Figure 4. Dk variation vs. temperature.

Table 4. Δτpd for 10 cm stripline, 25°C to 0°C

Coaxial cable dielectric materials have similar TCDk issues. Coaxial cables are typically much longer than PCB traces, which will result in a much larger ∆τ _{pd over temperature. Using two 1-meter cables with the same properties as shown in column 2 of Table 4 could result in a τ pd} mismatch of 25 ps when the temperature changes from 25°C to 0°C.

Table 4 assumes a constant temperature for a 10 cm trace length. In reality, the temperature may not be constant over the entire trace or coaxial cable, making the analysis more complicated than the case discussed above .

Recommendation : Understand the cost trade-offs between purchasing delay-matched cables and developing a calibration procedure to electronically adjust for delay mismatches.

In my experience, comparing coaxial cables of the same length and material from the same supplier has shown delay mismatches ranging from 5ps to 30ps. From discussions with cable suppliers, this range is a result of cable cutting, SMA installation, and Dk batch-to-batch variations.

Many coaxial cable manufacturers offer phase-matched cables with a predetermined matching delay window of 1ps, 2ps, or 3ps. As the accuracy of the delay matching increases, the price of the cable generally increases. To create a cable with a delay match of <3ps, manufacturers typically add several delay measurement and cable cutting steps to the cable manufacturing process. For the cable manufacturer, these added steps result in increased manufacturing costs and reduced yields.

Recommendation : When selecting cable materials, understand the trade-off between delay shift due to temperature and delay shift due to cable bending.

Bending a coaxial cable results in different signal delays. Cable vendor data sheets usually specify the phase error for a 90° bend at a specific bend radius and frequency. For example, at 18GHz, the nominal phase change might be 8° for a 90° bend. Using Equation 5, the calculated delay is approximately 1.2ps.

Variations in the mounting of PCB edge mounted SMAs can add delay mismatch between clock paths , as shown in Figure 5. Errors of this nature are not typically measured, so it is difficult to quantify. However, it is reasonable to assume that this could add 1ps to 3ps of delay mismatch between clock paths.

Figure 5. SMA installation delay mismatch.

One way to control the delay mismatch caused by SMA installation is to select an SMA with an alignment feature, as shown in Figure 6. Since SMAs with alignment features are typically rated for higher frequencies than SMAs without alignment features, and therefore cost more, there is a trade-off between the two. SMA suppliers often provide a recommended PCB-to-SMA launch pad layout for higher frequency SMAs. This recommended layout alone may be worth the extra cost because it can save board revision costs, especially when clock frequencies are greater than 5 GHz.

Figure 6. SMA with alignment feature

Recommendation : Understand the cost trade-offs between purchasing PCB materials with well-controlled batch-to-batch Ɛr and developing a calibration procedure to electronically adjust for delay mismatch.

Trying to match τpd between traces on multiple PCBs adds several sources of error. Four sources of error are discussed : delay matching vs. temperature; delay matching cable; delay matching vs. cable bending; and delay matching vs. SMA installation and selection. The fifth source of error is process-induced variation in Ɛr across multiple PCBs. Contact the PCB manufacturer to learn about process variations in _Ɛr .

As an example, FR-4’s Ɛr _may vary from 4.35 to 4.8. 6 For a 10-cm stripline trace on different PCBs, this range would produce a ∆τ _pd of up to 35 ps in extreme cases . Material data sheets for other PCBs give a smaller typical range of Ɛr. For example, the data sheet for the Rogers 4003C says that its Ɛr _has a range of 3.38 ± 0.05. For a 10-cm stripline trace on different PCBs, this range would reduce the possible ∆τ _pd to 9 ps in extreme cases.

Recommendation : Consider new PLL/VCOICs with <1ps skew adjustment.

In the past, data converter clocks were generated from multiple output clock devices. The data sheets for these clock devices specify the phase skew of the device, which typically ranges from 5ps to 50ps, depending on the IC selected. To the author’s knowledge, none of the multi-output GHz clock ICs on the market at the time of this writing have the ability to adjust the clock delay for each output.

As data converter clock frequencies greater than 6GHz become more common, single or dual output PLL/VCOs will become the clock of choice. The advantage of single output PLL/VCO clock IC architectures is that methods are being developed to adjust the reference input to clock output delay in steps of <1ps. The ability to adjust the reference input to output delay for each clock allows the end user to perform system-level calibration to minimize phase skew to less than 1ps. This system-level phase skew calibration has the potential to reduce all of the PCB, cable, and connector delay matching issues mitigated in this article, thereby reducing the overall BOM cost of the system.

本文讨论了可能延迟变化和延迟失配的几种来源。讨论表明，Ɛeff可能随温度、频率、工艺、传输线类型和线路间距而变化。同时表明，通过同轴电缆连接的多PCB设备会产生额外的延迟变化源。当选择材料以最小化大时钟树的相位偏差时，我们必须了解PCB和电缆Ɛr随温度、工艺和频率而变化的规律。对于所有这些变量，如果没有某种偏差校准，很难设计出偏差<10 ps的大时钟系统。此外，购买PCB材料、同轴电缆和SMA连接器以最大限度地减少相位偏差会显著增加材料成本。为简化校准方法并降低系统成本，IC制造商提供的许多新型PLL/VCO和时钟器件可实现低于1ps的延迟调整能力。

Table 5 summarizes the recommendations discussed in this article for minimizing phase deviation.

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