Integration of AI and EDA technology - accelerating high-frequency and high-speed design

Xi'an Station:

March 19 13:30-16:30

Grand Hyatt Xi'an, No. 12 Jinye Road, Yanta District, Xi'an

Beijing Station:

March 21 13:30-16:30

Beijing Parkview Hotel, No. 25 Zhichun Road, Haidian District, Beijing

The integration of AI and EDA is of great significance in the high-frequency and high-speed field. It can help improve design accuracy, optimize signal integrity, accelerate fault diagnosis and repair, and automate the design process to improve design efficiency and quality.

In this seminar, we will focus on sharing the application of AI technology in radio frequency design, SERDES design, memory design and semiconductor device modeling. At the same time, with the advancement of technology, multi-die technology is gradually becoming popular, and the UCIe interface design involved also has some areas that require special attention. We will provide you with relevant interpretations.

Reinventing Electronic Design Automation with Artificial Intelligence and Machine Learning

With the rapid development of artificial intelligence and machine learning, they have penetrated into every corner of electronic design automation (EDA). We will delve into how to optimize and innovate the EDA process through these cutting-edge technologies. Specifically explain how to use AI/ML to improve productivity in platforms including ADS, SystemVue and device modeling.

Power amplifier design based on AI/ML and measurement

Power amplifier design usually needs to be supported by measured load pull data. ADS can guide you to import, clean and visualize the measured load pull data, and use these data to optimize key indicators of power amplifier design, such as PAE, EVM, ACLR, etc. Through practical examples, you will learn how to improve power amplifier performance through load pull data and understand how to use this data to customize artificial neural network (ANN) models for nonlinear simulations.

UCIe Universal Chiplet Interconnect Interface Technology Simulation

High-performance computing is an important driving force for the rise of Multi-Die systems. The Multi-Die system can be used to achieve heterogeneous integration, and smaller chiplets can be used to achieve higher yields, smaller dimensions and compact packaging, reducing the power consumption and cost of the system, which can not only solve the performance demand in the AI ​​​​field that grows every two years The 800-fold demand can also address the huge demand in multiple industries for semiconductors with faster speeds, lower power consumption, and higher bandwidth. Dies communicate using the UCIe standard. In this demonstration, you will have an in-depth understanding of the chiplet's high-speed communication standard and how to simulate it. In addition, we will also explore how to use the intelligent design environment to easily calculate and optimize eye diagrams and bit error rates. (BER), contours and voltage transfer function (VTF), etc.

New SerDes and memory design flow

The rapid development of AI/ML, 5G and IoT devices continues to drive iterations of memory technology. Higher access speeds make memory design and verification more difficult. Memory interface signal integrity can be affected by crosstalk, reflections, and noise. Time budgets become tighter and error margins narrow. Increased power consumption may cause thermal problems that affect reliability. In this demo, you'll learn about the latest workflow solutions for SerDes and memory designs, helping you shorten the time from concept to simulation and verification.

Fast electromagnetic-circuit co-design

RF engineers use PCB boards and modules to implement system functionality at a lower cost than custom integrated circuit designs. With the advancement of technology, the chips, packages and three-dimensional components within the module have more complex processes and technologies. This makes electromagnetic co-design of circuits more difficult, and we will introduce a new approach to address these challenges to help RF engineers perform module integration in seconds or minutes.