2019 CCF Integrated Circuit Early Career Award winners announced, Associate Professor Jiang Li of Shanghai Jiao Tong University wins the award

The China Computer Federation (CCF) Integrated Circuit Early Career Award is established for young scholars who have worked for no more than 6 years, to provide support for the early careers of young scholars engaged in the field of integrated circuits. This is the only integrated circuit professional award in the China Computer Federation system. The first selection was launched last year. This year is the second year, and the grand announcement was made at the 11th National Testing Conference (CTC 2019). Moore Elite has sponsored the Early Career Award for two consecutive years.

After three rounds of reviews by seven international and domestic peer experts, Associate Professor Jiang Li from Shanghai Jiao Tong University was awarded the honor in recognition of his academic contributions in the field of integrated circuit test fault-tolerant design in the post-Moore era.

Associate Professor Jiang Li has been focusing on the research of integrated circuit testing and circuit fault tolerance technology. In response to the high cost of 3D chips, he first proposed the design and optimization method of the "pre-binding test" architecture of 3D chips, which was introduced into the IEEE standard P1838. In response to the high failure rate of TSV in 3D ICs, he first designed an extremely efficient TSV repair architecture and redundant resource sharing technology on adjacent chips in 3D memory, which refreshed the record of 3D memory repair efficiency. The following is an exclusive interview by Semiconductor Industry Observer with the winners, Associate Professor Jiang Li of Shanghai Jiaotong University, Secretary-General of the CCF Fault Tolerance Committee, Researcher Han Yinhe of the Institute of Computing Technology of the Chinese Academy of Sciences, and Mr. Zhang Jingyang, Chairman and CEO of Moore Elite.

"Teacher Jiang, you have been focusing on the research of integrated circuit testing and fault-tolerant technology. The "test before binding" architecture design and optimization method you proposed for three-dimensional chips has been introduced into the IEEE standard P1838. Can you introduce the research content and significance of this groundbreaking achievement?"

Three-dimensional chips are made by stacking and binding multiple chips in the vertical direction. They are the main way to improve chip integration and bandwidth in the post-Moore era. However, if any layer of chips fails, the bound chip will be scrapped, resulting in serious yield problems and high costs. If each chip is tested before being bound, the faulty chips can be eliminated. However, traditional test architectures have never considered supporting pre-binding testing.

To this end, we first proposed a test access mechanism that supports the test tasks of each chip before and after binding and allows the two test tasks to share test access resources, greatly reducing the cost of testable design; secondly, since the chip is not packaged before binding, the test pins are extremely limited. We optimized the test access architecture and test scheduling algorithm to enable the test tasks to run efficiently under the limited test pins, greatly reducing the test time cost. These works were adopted as the basis of the work of EJ Marinissen, chief scientist of IMAC, and he further introduced it into the IEEE P1838 standard.

Reducing test costs and improving yields are crucial for the final mass production of any cutting-edge chip technology. In addition to the pre-binding test architecture design work, the three-dimensional memory redundant repair resource sharing technology we subsequently proposed was adopted by the industry as a basic technology in public papers. For example, the three-dimensional memory repair technology recently cooperated with TSMC experts has once again refreshed the repair rate; for example, AMD used a chapter in the top computer architecture conference MICRO to introduce our three-dimensional chip vertical channel online repair technology, and one year after the paper was published, it took the lead in integrating three-dimensional memory into its GPU chip products. This series of work has received hundreds of citations in the EDA and testing fields, laying the foundation for the final three-dimensional chip testing, yield improvement and cost reduction.

"What difficulties and challenges have you encountered in your exploration of integrated circuit testing and fault-tolerant technology? What kind of support do you hope to receive in the future?"

Integrated circuit testing and fault-tolerant technology belong to the field of EDA, and require close cooperation with the industry. However, in the few years since I returned to Shanghai Jiaotong University to teach, I have found that it is difficult to survive in the research of integrated circuit testing and fault-tolerant technology. The main reason is that this research needs to be closely connected with the industry, and requires understanding of the needs within the industry, experience and financial support. Due to the backward overall development level of the domestic integrated circuit industry and the imperfect industrial chain such as EDA, we are faced with the dilemma of not being able to find funds, partners, and research problems with "industrial value". Although some cutting-edge research has been done (such as carbon nano transistors, single three-dimensional chips, and memristors), the results are often influential abroad, but no one cares about them in China.

Fortunately, through continuous exploration, divergence and communication, we have now started close cooperation with industry leaders such as Huawei and Alibaba in many different directions. Moreover, EDA is currently crucial to breaking through the bottleneck technology blockade, and the country and the industry also attach great importance to it. It will get better and better in this research field.

"We were deeply touched by Professor Jiang's sharing. As a company that provides professional services such as chip design, wafer fabrication, packaging and testing, what kind of support can we provide to young scholars like Professor Jiang?"

The difficulty of tape-out and verification mentioned by Professor Jiang is indeed a common problem faced by the academic community. The semiconductor industry is an industry with strong economies of scale. Often the top 20% of customers bring 80% of the orders. Therefore, foundries and packaging and testing factories are unwilling and difficult to serve small, fragmented customers. In particular, most of the school research projects are for research and verification, and rarely converted into mass production orders. Suppliers invest costs but do not make money, so there is less support for school research projects.

Moore Elite's mission is to "make it easy to make chips in China" and provide one-stop professional services such as "chip design, wafer packaging and testing, talent services, and enterprise incubation". Its customers cover 1,500 chip companies around the world. It currently has 300 employees worldwide and is growing rapidly. The value of Moore Elite's business model lies in "killing two birds with one stone" and "growing together with customers", that is, providing the same customer with one-stop professional services throughout its growth cycle, minimizing customer acquisition costs and transaction costs between links, and improving efficiency. At the same time, by aggregating supply chain orders, it strives to obtain better prices, delivery dates, and services for customers.

In order to accelerate the transformation of chip-related scientific research results in domestic microelectronics colleges and universities, Moore Elite has launched the "Moore Star" university plan for colleges and universities, providing colleges and universities with all resources of the one-stop docking platform, providing high-quality chip back-end implementation, tape-out, packaging and testing services, so that colleges and universities can focus more on technology development and technological innovation. Moore Elite currently has a chip design service R&D team of more than 150 people, an interface wafer factory technical service and supply chain operation team, and a packaging and testing engineering team to provide customers with high-quality, one-stop delivery. In response to the current severe shortage of supply in the market, in order to meet the chip packaging and proofing needs of small and medium-sized chip design customers including college customers, Moore Elite invested 50 million to build the Hefei Speed ​​Core Microelectronics Rapid Packaging Production Line, which was officially put into production in July 2019. Teacher Jiang and all domestic college teaching and research workers in semiconductor-related majors are welcome to use Moore Elite's chip design services and supply chain services to help the integration of industry and education.

"Teacher Jiang, do you plan to use your research results in commercial products in the future? What is your plan?"

At present, there is no plan to commercialize the research results in three-dimensional chips, mainly because the requirements for process and manufacturing are high, the investment is large, and it is not suitable for start-ups. There are opportunities for commercialization in the research results of neuromorphic and edge intelligent chip design tool chains based on memristor arrays. There are more opportunities in about 3-5 years. I agree with the view of Professor Kai Li of Princeton University, a member of the American Academy of Engineering: research is the process of converting money into knowledge, and innovation is the process of converting knowledge into money. At present, I still need to accumulate technical achievements until a technical barrier is formed, and cultivate a core team of doctoral and graduate students. The research results of neuromorphic computing chips must be implemented through tape-out, and the results of edge intelligence must be influential through open source. When the time for large-scale engineering and marketization comes, consider commercialization.

"It can be seen that Professor Jiang has made differentiated commercialization route plans for his different research directions. We wish the design tool chain of edge smart chips and other research results a smooth commercialization. I heard that Moore has made some positive explorations in this regard. Can you ask Mr. Zhang to share some of them?"

The semiconductor industry is a very special industry with a high degree of professionalism, detailed industrial division of labor, and a long time span. It takes a lot of effort and exploration to transform scientific research results into profitable commercial projects. Moore Elite currently supports the commercialization of scientific research projects from two main aspects. On the one hand, through chip design and supply chain professional services, sharing practical experience and R&D engineering resources, lowering the threshold for engineering realization and mass production, solving the challenges of landing caused by the lack of resources in various aspects in the early stage, and helping chip projects grow faster and more steadily; at the same time, we have also established the "Moore Semiconductor Index Fund" to cover seed round investments in chip companies, and also help early chip projects to efficiently connect with professional investors who "understand chips and invest in chips", supporting chip entrepreneurial teams to quickly start their business dreams.

"Teacher Han, you have been engaged in research on dedicated processor chips at the Institute of Computing Technology of the Chinese Academy of Sciences. You are an internationally renowned scholar in this field. As the Secretary-General of the CCF Fault Tolerance Committee, you are also one of the initiators of OpenBelt. What do you think of open source EDA?"

Specialized processors are different from general-purpose processors. They are oriented to specific fields and achieve advantages such as higher performance and lower power consumption through customized architecture and circuit design technology. In 2018, Turing Award winner David Patterson believed that domain-specific architectures will usher in the "golden age of architecture." The robot processors and space-borne processor chips that I am working on all belong to the field of specialized processor research.

When we proposed the OpenBelt initiative, we had a lot of discussions, and there has always been an important question pressing us: Who are the earliest users of open source EDA? Only by solving this problem can open source EDA and agile development really take off. My personal opinion is that dedicated processor chips may be the earliest important users of open source EDA and agile development, rather than the general-purpose processors that are currently in large quantities and widely used. General-purpose processors such as server processors, desktop processors, and mobile phone processors are the main force in the current chip field, but these chip markets are highly competitive and have extremely high requirements for performance and energy consumption. Open source EDA cannot meet the needs in a short period of time. Dedicated processors are different. Because their design is closely aligned with specific application requirements, they can make up for the shortcomings of EDA-generated circuit performance through innovations in system design and architecture. At the same time, open source EDA and agile development have the advantage of greatly reducing the development cycle, which is precisely the rigid demand of dedicated processor chips. Dedicated processor design must respond quickly to changes in applications, which is currently impossible to achieve in commercial EDA.

Open source EDA must be combined with agile development. The current design methodology (DA) solves the problem of large-scale design automation, making it possible to integrate billions of transistors in a single chip. The next generation of design methodology may pay more attention to the design cycle, that is, agile development, to meet the needs of more segmented and faster-changing applications and more chip types in the future era of the Internet of Things. Therefore, OpenBelt should consider building on the agile development process during the framework conception stage, such as choosing a higher-level design language and attracting more of the latest research results in artificial intelligence.

For OpenBelt to succeed, there needs to be a mechanism to attract active participation from academia and industry. Only when the chip design industry is committed to the continuous optimization of open source EDA tools and shares these results, can the open source EDA platform form a continuous source of power for continuous forward development, achieve breakthroughs in performance and ultimately achieve results .

"Teacher Jiang, what important technology trends did you see at the CCF Fault Tolerance Conference?"

The CCF Fault Tolerance Conference held a series of cutting-edge technology forums on chip and system test fault tolerance and design automation. I saw three important technology trends:

Chip security issues mainly include side channel attacks, hardware Trojans, and physically unclonable functions (PUF). With the advent of the 5G+IoT era and the development of the international situation, hardware security has become increasingly important. First, the advent of the 5G era has enabled the (intelligent) Internet of Things to expand from industrial-specific fields to broader consumer fields. Information and network security issues will extend to the physical world, directly affecting the property and lives of people and society. Secondly, based on the new international normal of confrontation between China and the United States and the United States and Russia, national security, industrial security, and information security have become major challenges. Therefore, trusted computing and hardware security will have an important impact on the country and society. This conference has multiple paper sessions and two technical forums involving the security and trusted computing of hardware and software systems; this direction will become a highlight and key discussion area of ​​the fault-tolerant conference in the future.

Future hardware design faces increasingly severe challenges. First, the complexity of hardware design continues to increase, and its development cycle and cost cannot keep up with the innovation of software and algorithms. For example, the rapid iteration and search of deep neural network structures often take a few months, while neural network-specific acceleration chips still take one and a half years. Secondly, hardware design cannot meet the diverse power consumption, performance, and size requirements. Although general-purpose processors have good programmability and adaptability, their energy efficiency is not high. In the future, domain-specific chips will shine. Agile design can quickly and automatically generate domain-specific chips with excellent performance and energy efficiency for diverse scenario requirements, which not only solves the problem of design cycle, but also solves the problem of adaptability, killing two birds with one stone. For example, the "algorithm as chip" design in the AI ​​field: given a neural network structure, quickly generate chips and software stacks. Agile design has been widely adopted in the software field, and has four characteristics in the hardware field:

In-memory computing and neuromorphic computing architecture is a radical non-von Neumann architecture, in which the storage unit itself is also "transformed" into a computing component, achieving "in-memory computing". Intel's Lori and IBM's TrueNorth two verification chips use 3D cross-point and SRAM respectively to achieve neuromorphic computing, and many startups are also engaged in industrialization. Memristors are a very promising way to implement neuromorphic computing.

Storage-class memory (SCM) based on new memory technologies is revolutionizing data storage architecture, and emerging memories have also been applied to new digital systems to increase speed, reduce power consumption, and efficiently execute AI. Phase change memory (PCM) has been actively promoted by Intel and Micron into SCM for persistent memory in the data center hierarchy to improve performance, reduce power consumption, and wake-up service time.

This year's CCF Fault Tolerance Conference also had a paper session and a technical forum to discuss the design of new memory. Our research group also published several cutting-edge results on neuromorphic computing represented by memristor arrays.

Since its birth, the cloud computing industry has maintained a rapid development momentum. The computing power of modern data centers has also been developing rapidly, and the scale of its equipment has been growing, becoming a basic service for the entire society. However, this trend inevitably poses a threat to the reliability of the system. In a large-scale server cluster, even failures that originally have a very low probability of occurrence will become a major threat in the cluster. Some hardware failures are likely to accumulate and spread in the system, causing damage to the server's operating system and upper-layer applications, and eventually causing the server to crash. For online cloud service nodes, server crashes mean a series of serious consequences such as business interruption and data loss. In order to meet these challenges, it is possible to build effective reliability mechanisms such as anomaly detection, root cause diagnosis, and fault prediction by building a performance detection, tracking, data development and collation framework for data center infrastructure and conducting large-scale data analysis.

In recent years, machine learning algorithms have developed rapidly, and their applications in various fields have achieved good results. In terms of data center reliability, there are also many works that use machine learning algorithms to detect or predict failures of computer components. For example, in the field of hard disk failure prediction, Microsoft has studied a variety of models based on machine learning algorithms that use logs generated by SMART technology to predict hard disk failures. In terms of memory failure prediction, companies such as AMD, IBM, and Intel have also studied the use of a variety of machine learning algorithms for memory failure classification and prediction. But in summary, research in this field is not mature, and there is still a lot of work to be done in terms of model generality, interpretability, data integrity, and other aspects.

There are two reliability forums at this CCF Fault Tolerance Conference, one of which is specifically for cloud computing and data center scenarios. I believe that more and more manufacturers will increase their research investment in this area.

"Teacher Jiang, is there anyone you would like to thank in particular at this moment?"

First of all, my doctoral supervisor, Professor Xu Qiang from the Chinese University of Hong Kong, was my mentor in starting my research. He had a profound influence on my academic style, trained my academic qualities, and laid a solid foundation for my academic skills.

Secondly, my collaborator is Professor Krish Chakrabarty, the Dean of the ECE Department at Duke University and an IEEE/ACM Fellow. Not only have we published several collaborative papers, but I also visited his laboratory for half a year. Under his guidance, I deeply realized the importance of combining theory with practice, and he was always able to solve extremely challenging research problems in cooperation with the industry. In my own research, I also collaborated with more than 10 departments and teams including Huawei, Alibaba, SenseTime, and DeepBlue Technology to produce valuable research discoveries. In addition, the research work of Professor Xie Yuan at UCSB and Professor Chen Yiran at Duke University also inspired me deeply. My work in the two main research directions of three-dimensional chips and neuromorphic computing was carried out under their inspiration.

Again, under the guidance of Professor Han Yinhe from the Institute of Computing Technology of the Chinese Academy of Sciences, I began to actively engage in academic services. CCF Fault-Tolerant Computing Committee, CCF YOCSEF gave me a great stage. Through continuous organization of activities, I honed myself, broadened my horizons, and created a display and communication platform for young scholars who are also young people. Thanks to the sponsor of CCF Integrated Circuit Early Career Award, Moore Elite and CEO Mr. Zhang Jingyang, for making it easier for China to make chips. Moore Elite is doing something very emotional.

The leaders and colleagues in my unit gave me a lot of help, which helped me adapt to the academic environment in China. Professor Liang Xiaoyao introduced me to Jiaotong University and gave me selfless help in the early stage of my career. When I first started working, I failed to get the Natural Science Foundation Youth Fund twice in a row. Professor Guo Minyi, Chen Guihai and Wang Xingbing, as well as Teacher Li Xiaowei from the Institute of Computing Technology of the Chinese Academy of Sciences, took the trouble to revise and correct my application repeatedly, which changed my inherent way of thinking and improved my writing skills. Professor Yang Xiaokang and Academician Mao Junfa helped me participate in government science and technology planning, which not only exercised my ability, but also gave me a clearer understanding of the current situation of domestic academic and industrial development and future development directions.

The key event was the US technology blockade against ZTE and Huawei. This event changed society’s perception of the security of integrated circuit design and other technologies, as well as the security of the supply chain, and prompted these high-tech companies to focus more on young scholars like me, which is a rare development opportunity at present.