Micron's view on the storage market

Source: The content comes from the public account "Xiangping Technology", author: Guosheng Electronics Team, thank you.

Micron Technology is an American company headquartered in Boise, Idaho, and was founded in 1978. Its main products include DRAM and NAND Flash. In the latest Q2 fiscal quarter of 2019, Micron's DRAM business accounted for about 64% of its total revenue, while NAND Flash revenue accounted for about 30%.

At its investor conference on May 23, Micron showcased its NAND Flash and DRAM technologies, as well as its future technology development plans.

Micron Technology has an excellent team and is growing. Strong team: Global talents drive innovation, and have been successfully included in the top 50 US patent list and Forbes' 2019 "Best Employers for Diversity". Recruiting talents: > 50% of new R&D employees have master's and doctoral degrees; > 60% have technical and industry experience; certified as an excellent workplace in 2018. Approach: Build a better team by promoting STEM education, increasing curiosity, promoting STEM education and collaborating with top universities around the world.

We have a global technology presence, provide world-leading innovation and execution, and accelerate core technologies through disruptive innovation.

The production site has strong development capabilities: core technology research and development is carried out at the Idaho base in the United States, and the Fab factory production capacity is distributed around the world. Japan is mainly used to produce DRAM, Singapore mainly produces NAND Flash, and the innovative 3D Xpoint is in Utah, USA. Packaging is completed in Taiwan Province, and Virginia, USA meets the needs of the automotive market.

• Japan - DRAM

• Singapore - NAND

• Utah, USA—3D XPoint TM

• Taiwan Province——Packaging

• Virginia – Car

Core technologies: The most comprehensive technology portfolio in the industry - continuously meeting customer needs

DRAM/3D NAND/NOR/3D XPoint TM/3D Packaging/Emerging Technologies

Micron has made rapid progress in ramping up 1Znm production, and its competitive position in 1Znm DRAM is constantly improving. Micron will continue to promote 1Znm DRAM technology and 16Gb LPDDR4. After 1Znm technology, there are 1α, 1β, and 1γ. In the process from 1Znm to 1γ technology, Micron will continue to evaluate the cost-effectiveness of EUV process DRAM and use EUV when appropriate.

Trends in DRAM evolution: DRAM expansion faces obvious challenges in industry trends: Gb/Wafer increase is more difficult; node conversion costs challenge the final benefits; capital expenditure intensity continues to grow.

DRAM process evolution: driving technological leadership

Continue to reduce costs and improve performance:

Optimizing lithography methods: Challenges of EUV mode for advanced DRAM applications

Micron uses multiple patterning technology to optimize future DRAM nodes. Multiple patterning technology is a strong strategic advantage. It has verified the mature technical capabilities and cost efficiency of 1Znm to 1γnm. It is evaluating EUV for DRAM production.

128-layer NAND, the progress of gate technology (Replacement Gate) has strengthened the confidence of node migration. Micron will develop towards 128-layer 3D NAND, which is a 64+64-layer structure. In order to make NAND Flash continue to play its advantages in performance, capacity, size, etc., Micron will transition from Floating Gate to gate technology in 128-layer 3D NAND technology, and continue to use CMOS architecture under array technology. Achieve leadership in chip size, sequence, write performance and write energy/bit.

NAND Evolution Trends: Improving Leadership through Technology Transformation

NAND Flash technology has evolved from 2D to 3D, driving the increase in unit wafer capacity (Gb/wafer).

After 64 layers, the rate of NAND Flash capacity increase and cost reduction slowed down.

Time to mature DRAM and NAND production cut by more than half

Date: 2019-05-23

Company Participants:

• Farhan Ahmad, 'Investor Relations'

• Scott J DeBoer, 'Executive Vice President, Technology Development'

• David A Zinsner, 'Senior Vice President and Chief Financial Officer'

• Scott J DeBoer, 'Executive Vice President, Technology Development'

Good afternoon. I'm Scott DeBoer, Executive Vice President of Technology Development at Micron Technology.

Welcome to this webcast as we all focus on how we accelerate memory and storage innovation at Micron. Today, I will be demonstrating key technology updates. Last year's Micron Analyst Conference focused on Micron's team, our core technology innovation, and our strong focus on improving our execution, which will continue to strengthen our overall competitive technology position.

I will start with an update on the team and our focus on delivering core technologies for the company. We are proud of our technical team, working to develop technologies that will drive our company's products in the future. We believe our global talent is a significant competitive advantage that will drive our innovation. We are very proud to be recognized as a top 50 company in terms of U.S. patents and to be recognized as a top employer for diversity.

We will attract the best talent in the world to join Micron. We will use a person's educational qualifications and industry experience as indicators and focus on raising the bar. We have a great workplace that helps us attract new talent to Micron. In addition, we support STEM education related to artificial intelligence, both in K-12 and in college, and work closely with top universities around the world.

On the diversification front, I'm also pleased to note that approximately 50% of the students who participated in the R&D internship program in fiscal 2018 remain. We continue to strengthen our core R&D capabilities and BOISE key talent and infrastructure additions. Our BOISE team is focused on early technology investigations in our core memory products as well as more disruptive technologies. In addition, we have also directly strengthened our R&D efforts to support the production base by adding talent and infrastructure to support faster execution of future technology deliveries.

Our global R&D model is optimized to efficiently execute disruptive technologies while ensuring we have sufficient capacity directly within our production facilities to deliver world-leading technology qualifications and yields. This two-pronged approach to technology development not only allows us to execute different stages of development programs in the most efficient and flexible environment, but also allows Micron to uniquely leverage our diverse global talent base. This global technology team drives our resources to focus on delivering differentiated technologies that support the needs and requirements of our customers across a variety of different businesses. Power, performance, density, latency and cost of memory and storage solutions.

As I mentioned earlier, today the opportunity for differentiation in our products is greater than ever. Whether it's DRAM, NAND, 3D XPoint or other emerging memory technologies, our teams are focused on delivering unique capabilities to our customers. A rich portfolio of products and solutions addresses the key needs of our customers. Whether it's power, form factor, performance, reliability or other attributes, we meet the challenges we face. We work with customers across the range of markets shown in this slide to design memory and storage solutions that continue to deliver.

Now, I will move on to detailing the specific feature technologies that we are bringing to market in partnership with customers. We continue to have the most comprehensive technology portfolio in the industry, supported by the global talent and enterprise infrastructure that I described in the previous slides. Today, I will provide an update on NAND and DRAM technology progress since last year's analyst meeting.

We will significantly improve our competitive position in 2018, with a gap of approximately 10% to 15% behind the best competitor. I will show our progress in the next two slides, and our team is always committed to closing any technology capability GAAP gap by the best competitor. This year, we will launch the industry's first LPDDR4 16-gig monodi solution on our 1z nanometer technology. This leading mobile memory product is currently in customer qualification.

We are currently in the process of ramping to 1z technology, and I am pleased with the progress we are making. I will discuss our execution in detail in a few minutes. Our focus on the 1z technology node includes improving cost and enhancing product performance. Some examples are shown in this slide, including important power indicators of DRAM performance in mobile devices running common applications, such as playing music and watching YouTube videos.

As shown, we delivered superior power performance compared to our 1z node competition, similar to what we accomplished at our 1X and 1Y nodes. We will continue to improve our competitive position as the 1z node ramps, but we recognize we have a long way to go and we will continue to focus on cost and performance leadership. Overall, when looking at industry trends on this slide, there is a clear slowdown in DRAM evolution, both from a "bits per wafer growth" perspective and a "cost per bit reduction" perspective, as technology challenges lead to lower levels and improvements at successive nodes.

As the CapEx intensity associated with scaling continues to grow. The cost of not transitioning is challenging the benefits of scaling at the end goal. While the trend towards lower bit growth rates per node and less cost reduction per node is very clear, certainly we will not see the type of node-to-node improvements that have occurred historically. Our teams remain focused on the difficult task of delivering future nodes that can provide viable returns.

We believe that our combination of global talent and extensive DRAM experience makes Micron unique in being able to identify innovative ways to deliver viable future technology nodes despite the obstacles before us. As we look at the DRAM technology roadmap. We are currently focused on four nodes and at different stages of development. Beyond our one better node, our focus is on identifying viable solutions given the physical and cost difficulties that challenge nodes present.

I'll discuss this more in the next few slides, but lithography is not the fundamental DRAM scaling limitation. Micron's pattern multiplication technology is a strategic advantage and it's something we intend to continue to leverage over the next several DRAM nodes. The chart in the slide shows the relative cost structure of multi-patterning with EUV as a function of future DRAM nodes. The technology was initially introduced by Micron and we continue to advance the cost structure and technology capabilities of multi-patterning lithography processing.

We are confident in the technology capabilities and cost based on the development work we have completed. With our 1-gamma node, the efficiency of our multi-patterning approach to the 1z node. That said, we are evaluating EUV lithography for DRAM in an ongoing process to ensure that we are ready in terms of technology capabilities to improve to a point that is fully consistent with our roadmap. When EUV performance is favorable to Micron, we will be ready for EUV implementation. As mentioned above, we have been looking at options for EUV DRAM In this chart, you can see the evaluation for advanced DRAM nodes.

Well, EUV is certainly viable in terms of process capability at certain levels on the 1z and 1-alpha nodes. Our proprietary multi-patterning technology is still significantly superior in terms of cost to the EUV exposure option for these nodes. For more advanced nodes, EUV can reach overall cost parity at very low exposure doses, but the pattern quality is unacceptable under these conditions. Alternatively, if used with very high exposure doses, the pattern quality can be improved to the point where it may be used, but in this case the cost is significantly higher than the multi-patterning alternatives.

Given these factors, we do not plan to implement EUV in the near future, but we will continue to focus on the sweet spot as the technology advances. Similar to DRAM, I discussed our competitive NAND progress at last year's analyst meeting. We have made tremendous progress since 2013, with our leading technology approximately 60% of the number of gigabytes per wafer, and our most advanced competitor was competitive with 96-layer CMOS based array technology in 2018. Our continued progress over the past year will be shown in the next few slides.

We have made solid progress in replacement gate technology over the past year, providing confidence in our transition strategy. While we are currently focused on 128-layer technology as shown on this slide. Our overall strategy involves first building a pilot line for a lower-layer gate technology in preparation for the 128-layer ramp. Our success in achieving replacement gate technology NAND and achieving yield with this pilot line has greatly increased our confidence and experience as it relates to executing at the 128-layer node on a competitive timeline.

As a reminder, our RG technology is a unique combination of industry-leading CMOS in an array concept, combined with our third generation array stacking technology and charged RAP [ph] cell technology. This combination of technology features enables the right performance and right energy bit in the leading and die size order, which are key attributes for the markets we serve. Similar to DRAM, CapEx intensity and process complexity are combining to slow bit-per-wafer growth and limit the rate of cost reduction in the next few years. After planar to 3D, the gains from process advancements are diminishing.

After 64 layers, bit-per-wafer growth will slow as the industry focuses on more traditional transitions from one 3D node to the next, rather than the planar to 3D transitions we've seen in the past. As shown in the chart, in this slide, cost reductions per node have plateaued over the past few years as a direct result of capex intensity and process complexity. The roadmap and development for NAND is ongoing, in addition to our initial replacement gate transition for the official replacement at the 128-layer node.

We believe we will be very well positioned to drive cost and performance leadership as we converge from floating gate to replacement gate transition and focus on delivering next node NAND with TLC and QLC replacement gate. The new Micron will take our performance to even higher levels and of course, continually challenging ourselves to improve operational execution is a key aspect of this. I'll end today with an example of how we are working to improve execution at Micron. Following this, the time it takes to bring a technology to mature yield was originally developed as a key execution metric. Reducing this time to baseline levels and beyond for both DRAM and NAND has been a focus for our development and manufacturing teams.

As shown in this slide, we have made significant progress over the last few years and we have increased our yields, reducing mature yields by more than half for both DRAM and NAND. The significance of this execution is amplified given the increased complexity, difficulty and scaling we face in other industries. This is a result that the Micron team is very proud of. Our focus on innovation, technology acceleration and execution over the last few years has led to significant advances in our overall competitive technology position. As I said a year ago and still believe today, Microns is in a better position with more core technology capabilities than at any time in the past 25 years. With that, I would like to thank everyone for participating in today's webcast and open the door to questions.

Q: Maybe in persistent memory is a topic of conversation for a lot of AI applications in the data center is that 3D intersection of your solution or do you have other products and development that might fall into the category of persistent memory.

A: Yes. We certainly have 3D crosspoint as one of our solutions at that application stage. We are developing other products with different emerging memories. And there are also some applications that can be met by a combination of standard year-end requirements. Those are sticking around from the demand.

Q: Okay, just in terms of the -- maybe in terms of the cost of development, you can take advantage of the fact that there's enough similarity between 3D crosspoint NAND and DRAM that you could [ph] use some of your development for 3D crosspoint NAND.

A: There are some similarities, but probably, you know, we've actually been dealing with 3D intersections for a long time, so while there are some toolset similarities, the technology is actually quite different. So NAND or expertise

The work that we've done on NAND has not increased the 3D crosspoint capability, but it's still a long development process that started at MicronTech [ph] many years ago.

Okay. First one, Scott, you mentioned some data points on EUV. I'm just curious based on that EUV 3400B. So when should we hear your results on the deceit [ph] version R&D, because ASIMO [ph] I've talked about significant advancements, should we wait until next year for the same update or should we be able to come back and give us an update? I have a follow-up.

Yes. Just to be clear, our assessment of EUV and our assessment is really based on the full roadmap EUV not just 3300B. If you look at this pattern technology, probably why you [ph] asked the question, 3300B is very similar from a resolution point of view to the next pair of tools, but as we look at the roadmap, we'll look at where the intercept point is based on the throughput of the latest tool capabilities. I think you also have a follow-up question, right.

Q: When you change the underlying NAND technology, are there any intellectual property licenses to third parties?

What should we consider?

A: No. We have a strong IP position in NAND technology with over 40,000 patents historically. Our IP related to NAND technology is very strong.

Q: You mentioned that the transition from 2D to 3D created a lot of bit growth but now that the transition is over, we are now doing the normal iterative node-to-node transition inside 3D which is going to be a little slower. I was wondering if you could talk about this in a little bit more detail, how much slower each node will be and the associated cost reduction, how to balance each node? Thank you.

A: I can talk about the near term and maybe just generally what we're seeing in the industry, but generally speaking the cost reductions that I showed have been pretty much flat over the last couple of years.

I think NAND, like DRAM, is going to be a very significant challenge for the industry to have this product cost reduction even level, so probably continue to come down some. If you just look at 3D technology, as you go from -- through these first few nodes, you went from our 32 layers to 64 layers, we basically doubled. That was a significant improvement. As we get into the hundreds of layers, we're looking at what percentage increase is going to be the next node for us as an industry, the percentage increase is going to be less.

If you just look at where we went from 96 layers to the next node that we talked about today, 128. Just the mass increase in bits in the same area or lower, when we came from planar, the increase was very substantial. When we went from planar at 15 or 16 nanometers to 64 layers. The bit capacity increase per wafer was huge but obviously, the historic increase was huge during this transition.

Q: And for 128, what kind of first application do you see?

A: Absolutely. Our end markets generally won't change significantly, we have mobile products, we have SSD products, we will work with customers to find the best fit, but I wouldn't see a big change there.

Yes. I want to build on that last kind of comment. I think last quarter or even the quarter before the comment or so, it was going to be a challenge from a cost-down perspective. So I'm curious, first of all, how should I think about that? And I think you even mentioned the fact that it's been fairly limited, the implementation of that process node in your portfolio, and how we think about the progression from there to the 1YY process node with replacement gate, how do you -- how do you expect to shorten that cycle? I mean try to get a sense of how long -- first implementation of gate technology might be a little bit of a cost disadvantage?

Yes , sure. It's a good question, and there are several parts to it, as you mentioned, what we said before is that the 128-layer node will not provide the same cost advantage, in part because we came from FG's 96-layer node. It was really special from a cost perspective. So when we go to our 128-layer node and talk about the benefits, which are not substantial during this time, we really are not saying that our 128-layer node will be that much worse than our competitors.

It's really that we're coming from a very strong place, we had a big capital change and involvement in the switch from FG, RG so we think our parts will be competitive at the 128 level, it's not going to be the kind of cost reductions we've seen before node to node. So think half of what we got at the prior node. As we go beyond that, we're going to be focused on trying to get industry competitive cost reductions relative to our business, anticipating that those technologies that are beyond that will have mature yields at the prior node. Having better commonality in the toolset allows us to drive a good cost reduction path.

Q: And then here's a quick follow-up. I'm curious about some of the things that you talked about in terms of the technology itself down to the chip level, but I'm also curious from a product perspective or a roadmap perspective for their stuff, I'm curious about the NAND Flash side, the commercialization of NVMe enterprise, SSDs, or even 3D Xpoint, any changes in the roadmap for those solutions. Thank you.

Yes. As we mentioned today and previously, we certainly view the 128-layer node as not a complete portfolio node, so there will be significant changes at the 128-layer node in terms of changes. As we look further out and our entire portfolio is complete, we will be in a stable position on the next node portfolio. There will certainly be 3D Xpoint products in the market at that point, and we will have other opportunities in NVMe and other areas, we didn't announce any of those today, but I think all of those things will be carried by our second-generation gate technology.

I guess first question, I think with 3D Xpoint, we've been focused on opportunities in data center servers and less focused elsewhere. I'd love to hear if those opportunities are outside of the server market? What's the ramp timeline like in those geographies?

Yes . We didn't announce any new products today, and we've talked about in the past that we do see opportunities for 3D Xpoint, both in mobile, in the data center, in a variety of different applications, and we think those applications will continue to expand, but nothing new to talk about today, but we are absolutely focused on product creation and creating value with this unique technology that Micron and Intel have created and being well positioned for the next few years, and that's a more important part of our business.

Okay. Thanks. Thanks. Thanks. Thanks.

A: Yes, of course. So, obviously, Thursday evening we were banned from exporting Huawei's institutional [ph] products, and there was an expectation that a special license would be issued -- that would be announced on Monday.

But the licenses are really specific to supporting installed products or phones that have been sold. So when we are another, this has minimal impact on us, so as of Thursday evening, we are not shipping to Huawei. Today [ph], if you looked at the 10-Q for the first and second quarter, Huawei was 13% of our revenue. Obviously, there will be a financial impact on that, and we will update you on the earnings call.

So we're not going to update anything immediately related to that. At this point, we obviously want a quick resolution, but at the same time, we're actively focused on the rest of the customer base, which of course needs to be supported and serviced, as well as all of the initiatives that we're talking about, like Scott talked about our technology and cost, improving our mix. All the while, I would say really focused on management, the company being economically disciplined. Again, we want a quick resolution to this, but we don't know much more than -- I think than others do, so we just have to wait and see how it goes.

Q: I'm asking on behalf of Tim Arcuri. Scott, so I understand you're kind of saying no EUV in the short term, but you

You've been exploring it as well. And in terms of making a decision on ultimately going to EUV at future nodes. How much do you think about whether you have to use EUV at future nodes?

A: We are looking for one of the benefits of what we talked about last year about how we set up our development process is now going a step further and doing more early development preparation at the node, which has been part of what has helped us improve our competitive position over the last few years.

So I think we have enough time to get ahead of a given node at least two or three years in advance. They're going to want to go to volume production for a variety of reasons. I think, we're very confident over the next few years. We also believe that we're closely involved and working on EUV technology and making sure that, when we need it, we have that runway. Multi-patterning technology over the next few years is something that's clearly in our business strategy that we're in good shape and we're going to continue to focus on it.

Q: I guess for the 128 layers, are you still considering stacking or are you considering a non-stacked version?

A: Okay. That's -- we're not going to talk about the technical details. We've been running stacked NAND technology successfully for multiple generations. Today, I told you we're going to finish at 128 layers. It's -- it's clearly the direction to extend the technology into the future. Exactly how we build to 1yy and beyond, talk more about it as we get closer to it.

Thanks for the follow-up. As you go to the 128-layer node on NAND and then to 1yy and 2xx, what happens to your wafer cycle time through the fab? Does it go up, down, or stay the same?

A: The whole cycle time depends on how much NAND really [ph] wants to go up because fundamentally increasing the number of layers is more films, more wafer complexity. But at the same time, we are working with all of our key suppliers to make sure that we have the right solutions in place to minimize the amount of time that is increasing or decreasing the amount of cycle time in certain steps. So our focus is obviously on minimizing the amount of increase in cycle time node to node and we do that by working with our suppliers and by innovating ways to change exactly how we build NAND to make sure that it's as efficient as possible. So it's going to go up some but we're absolutely focused on mitigating that as much as possible.

Yes. On DRAM, you've described a couple of generations, and it sounds like all of them are -- are they related to line scaling. Are you looking at any alternative future nodes that are more exotic than line, and are you scaling at the same time -- just like the way NAND scaled from going to 3D, are there other DRAM options?

Yes. DRAM is very complex in terms of -- there's not an obvious solution on NAND where you just flip it on its side and build it. So we're looking at a lot of ways to build DRAM more efficiently in the future. And like we talked about before, looking at different types of memory technologies. So there are aspects that we're definitely looking at, and we feel we have some interesting things, and we talked about some interesting things at the investor conference the other day, relative to emerging memories and the types of applications that can fit in, but we're not talking about any specific new DRAM architectures today.