Industry Observation | China's semiconductor packaging and testing industry will usher in spring

According to Gartner data, the global semiconductor industry revenue was US$420.4 billion in 2017, and the packaging and testing industry revenue was US$53.3 billion, accounting for 13%. Yole data shows that except for the industry surge in 2014, which led to a slight decline in 2015, the global packaging and testing industry has maintained a steady single-digit growth, and is expected to continue to maintain a year-on-year growth of 4.5% in 2018.

Figure 1. Global packaging and testing industry market size forecast (US$ billion)

Data source: Yole, China Fortune Land Development Industry Research Institute

The test and packaging industry is the driving force for China's semiconductor industry to catch up with the world. According to statistics from the China Semiconductor Industry Association (CSIA), the total sales of China's integrated circuit industry in 2017 was 541.1 billion yuan, of which the packaging and testing industry accounted for 188.97 billion yuan, accounting for 35%, a year-on-year increase of 20.8%, far exceeding the international growth rate of 4.5% in the same period. It is expected to reach 225.1 billion yuan in 2018, a year-on-year increase of 19.1%.

Figure 2. China's packaging and testing industry market size forecast (100 million yuan)

Data source: CSIA, China Fortune Land Development Industry Research Institute

Semiconductor packaging Refers to the process of processing wafers into independent chips according to product models and functional requirements. The packaged chips have four major functions: power transmission, signal transmission, heat dissipation and protection. Semiconductor testing Is to ensure the integrity of the delivered chips, which can be divided into two stages: one is the wafer test before entering the packaging, which mainly tests the electrical properties; the other is the IC finished product test after packaging, which mainly tests whether the IC function, electrical properties and heat dissipation are normal. Gartner statistics show that packaging and testing links account for 80%-85% and 15%-20% of the market share respectively.

Figure 3. Main functions of packaging test

Data source: China Fortune Land Development Industry Research Institute

The main process of semiconductor packaging and testing includes film pasting, grinding, film removal and re-film pasting, cutting, wafer testing, chip pasting, baking, bonding, testing, lamination, electroplating, pin cutting, molding, finished product testing, etc. The core of packaging is how to connect the chip I/O interface electrodes to the entire system PCB board. Bonding is the key link . That is, use wires to connect the welding points on the chip to the welding points of the package shell, and the welding points on the shell are connected to the wires in the PCB, and then establish electrical connections with other parts.

Figure 4. Packaging test process

Data source: Top Industry Research, China Fortune Land Development Industry Research Institute

In the semiconductor industry chain consisting of three links: chip design (Fabless), wafer manufacturing (Foundry), and packaging and testing (OSAT), packaging and testing is located at the downstream.

Figure 5. Semiconductor industry chain

Data source: China Fortune Land Development Industry Research Institute

Competition between IDM and OSAT business models: IDM (Integrated Device Manufacture) and OSAT (Outsourced Assembly & Test) are the two main models in the current semiconductor packaging and testing industry. IDM companies have their own brands, and their business scope covers design, manufacturing, packaging and testing, and even includes sales. OSAT companies do not have their own brands and provide packaging and testing foundry services for design and manufacturing customers.

The IDM production model is usually adopted in the early stages of the development of the semiconductor industry. Under this model, manufacturers need to invest large amounts of money to build production lines, which has the disadvantages of heavy assets and high risks. With the explosion of demand for smartphones and other products, the changes in downstream terminal demand have accelerated, and the benefits of the IDM model have gradually declined. The continuous growth of light-asset design companies and the overflow of orders due to insufficient internal production capacity of IDM companies have driven the rapid development of OSAT companies. Gartner data shows that the industrial scale of the OSAT model has exceeded that of the IDM model since 2013. The OSAT+Foundry model avoids large construction capital investment while meeting the market's demand for miniaturization, stronger functionality, and high customization. It will be the main model for the future development of the semiconductor industry.

Figure 6. Changes in OAST and IDM market share (percentage)

Data source: Gartner, Amkor, China Fortune Land Development Industry Research Institute

In the process of OSAT surpassing IDM, some IDM companies have transformed into fabless design companies. For example, AMD spun off its wafer manufacturing business in 2012 (and later established GlobalFoundry), and spun off part of its packaging and testing business in 2016 (selling 85% of its equity to Tongfu Microelectronics), completing its transformation into a fabless design company.

As the most critical technology in the testing and packaging industry , there are four types of bonding connection methods , including wire bonding, solder ball connection, solder ball flip-chip connection and TSV silicon through-via connection. Wire bonding has long been dominant. From a technical point of view, flip chip (FC) technology is gradually replacing wire bonding. From an industry perspective, the packaging and testing industry is undergoing a transformation from traditional packaging (SOT, QFN, BGA, etc.) to advanced packaging (FC, FIWLP, FOWLP, TSV, etc.). Advanced packaging technology is highly efficient, and chips are evolving towards smaller and thinner directions, with lower amortized costs, which can achieve better cost performance. The disadvantage is that the initial investment is large, and economies of scale are needed to reduce costs.

According to Yole data, the output value of advanced packaging exceeded US$20 billion in 2017, accounting for about 38% of the global industry. By 2020, the output value is expected to exceed US$30 billion, accounting for 44%. Among them, FC technology accounts for the largest share in the advanced packaging market. In 2017, the FC market size reached US$18.6 billion, accounting for 34% of the world and 90% of the total value of advanced packaging and testing. From 2017 to 2022, the global advanced packaging 2.5D&3D, FO, FC and other technologies are expected to have a compound annual growth rate of 28%, 36% and 10% respectively, which is much higher than the average growth of 4.5% in the packaging and testing market.

Figure 7. Global advanced packaging market size (billion U.S. dollars)

Data source: Yole, CICC, China Fortune Land Development Industry Research Institute

According to VLSI data, advanced packaging shipments accounted for about 35% in 2017. VLSI predicts that the speed of downstream customer groups shifting to advanced packaging will temporarily slow down, and traditional packaging will still dominate. For Chinese companies, most of whose production capacity comes from traditional packaging, this will help domestic packaging and testing companies to further increase their market share.

Figure 8. Global packaging scale: advanced packaging and traditional packaging

(millions of 12-inch wafers)

Data source: VLSI, CICC, China Fortune Land Development Industry Research Institute

China's advanced packaging market output value accounts for a relatively low proportion of the world's total, but it is growing rapidly and its share is expanding. According to Yole data, China's advanced packaging output value was US$2.9 billion in 2017, accounting for 11.9% of the world's total, and will reach US$4.6 billion by 2020, accounting for 14.8% of the world's total. Data shows that Chinese packaging and testing companies accelerated their production capacity in the advanced packaging field in 2018, with a growth rate of 16%, twice the global rate. After acquiring STATS Semiconductor, Changdian Technology's advanced packaging product shipments accounted for 7.8% of the world's total (in 2017), ranking third, second only to Intel and Siliconware Precision Industries.

Figure 9. Global advanced packaging scale and China’s advanced packaging scale (billion US dollars)

Data source: Yole, China Fortune Land Development Industry Research Institute

The demand for high integration, high pin density, small size and low cost of semiconductor chips has promoted the development of semiconductor packaging technology. The development of semiconductor packaging technology can be divided into four stages.

Figure 10. Semiconductor packaging technology evolution path

Data source: Yole, China Fortune Land Development Industry Research Institute

The first stage (before 1970): direct-insertion packaging, mainly DIP.

The second stage (1970-1990): The four major packaging technologies of SOP, SOJ, PLCC, QFP and PGA technology derived from surface mount technology.

The third stage (1990-2000): Advanced packaging technologies such as ball grid array (BGA), chip size package (CSP), and flip chip (FC) began to emerge.

The fourth stage (2000-present): From two-dimensional packaging to three-dimensional packaging, advanced packaging technologies such as wafer-level packaging (WLP), through silicon via (TSV), and 3D stacking have been developed from the technical implementation method. From the semiconductor product level, new packaging methods such as system in package (SiP) have emerged. The development of packaging technology has further improved the integration and performance of chips.

Next, we will mainly introduce several advanced packaging technologies and their applications.

▼ Flip chip technology FC - half of the current advanced packaging industry

As the earliest advanced packaging technology, FC has the following three advantages over traditional packaging:

(1) Superior thermal performance and improved heat dissipation capacity: The back of the chip can be effectively cooled, and the shortest loop provides a low thermal resistance heat sink.

(2) Enhanced electrical performance: reduced contact resistance and increased frequency, up to 10-40 GHz.

(3) Reduced size and enhanced functionality: Increased I/O number and improved reliability.

FC technology connects the chip to the substrate through a bump. It gets its name because the chip is flipped over to allow the bump to be directly connected to the substrate. The chip active area faces the substrate, and the chip and substrate are interconnected through solder bumps arranged in an array on the chip without the need for wire bonding.

Figure 11. Flowchart of flip chip FC

Data source: Wikipedia, China Fortune Land Development Industry Research Institute

Bump is the only channel for electrical connection between FC and PCB, and is also a key link in FC technology. Bumps are divided into two categories: solder and non-solder. According to the manufacturing method, they are divided into solder bumps, gold bumps, and polymer bumps. The bump process directly affects the feasibility of flip-chip technology and the reliability of performance. Solder balls are the most common bump materials, but according to different needs, gold, silver, copper, and cobalt are also options. For high-density interconnects and fine-pitch applications, copper pillars are a new option. During connection, solder balls will diffuse and deform, while copper pillars will maintain their original shape very well, so copper pillars can be used for denser packaging. Copper pillar technology is currently developing the fastest.

Figure 12. Bump schematic diagram - two types: Solder and Cu Pillar

Data source: ASM Pacific Technology, China Fortune Land Development Industry Research Institute

The most commonly used bump production technology is electroplating bump technology, while innovative bump technologies include wafer-level solder ball transfer technology and jet bump technology. Among them, jet bump technology has extremely high efficiency in making solder bumps, with a jet speed of up to 44,000 drops per second, and is expected to become an industrial standard.

Figure 13. Wafer-level solder ball transfer technology

(Wafer Level Solder Sphere Transfer)

Data source: PacTech, China Fortune Land Development Industry Research Institute

Figure 14. Solder Sphere Jetting

Data source: PacTech, China Fortune Land Development Industry Research Institute

According to Yole data, the shipment of integrated circuits using FC technology will maintain steady growth, and wafer production capacity is expected to expand at a compound annual growth rate of 9.8%, reaching 28 million 12-inch wafers by 2020. The terminal applications of FC technology are mainly computing chips, such as CPU, GPU and chipset applications for desktop and laptop computers.

Figure 15. FC market development trend by bump type (percentage/10,000 pieces)

Data source: Yole, CICC, China Fortune Land Development Industry Research Institute

▼ Wafer-level packaging PIWLP, POWLP—development towards miniaturization and high efficiency

The conventional chip packaging process is to cut the whole wafer into small grains before packaging and testing, while wafer-level packaging technology (WLP) is a technology that packages and tests the whole wafer and then cuts it to obtain a single finished chip. The size of the packaged chip is exactly the same as the bare die. Wafer-level packaging has two major advantages:

(1) Distribute the chip I/O over the entire surface of the IC chip, so that the chip size reaches the limit of miniaturization.

(2) Package, age, and test numerous chips directly on the wafer, thereby reducing conventional process flows and improving packaging efficiency.

Figure 16. Schematic diagram of conventional wafer packaging (top) and wafer-level packaging (bottom)

Data source: Semiconductor Engineering, China Fortune Land Development Industry Research Institute

PIWLP: Since all the pins are located under the chip, the number of I/Os is limited, which is called wafer-level chip scale package WLCSP or fan-in wafer-level package FILWLP. The characteristic is that the package size is the same as the die size, and it is currently mostly used for low-pin-count consumer chips.

As the number of integrated circuit signal I/Os increases and the size of solder balls decreases, the PCB's adjustment requirements for the size of the integrated circuit package and the position of the signal output pins cannot be met, thus deriving POWLP.

POWLP: Fan-Out technology refers to extending the I/O bumps to the periphery of the chip through the redistribution layer (RDL), which can meet the requirements of increased I/O numbers without making the solder ball pitch too small to affect the PCB process. In addition, RDL layer wiring is used instead of the IC carrier required for traditional IC packaging, which greatly reduces the overall package thickness and meets the thickness requirements of smartphones.

Figure 17. Fan-In (top) and Fan-out (bottom) diagram

Data source: IEEE, China Fortune Land Development Industry Research Institute

Figure 18. Application of Fan-out technology in smartphones

Data source: Yole, China Fortune Land Development Industry Research Institute

FIWLP and FOWLP have different uses, but both will be mainstream packaging methods in the future. FIWLP is mainly used in analog and mixed signal chips, and some wireless interconnects and CMOS image sensors are also packaged using FIWLP technology. FOWLP will be mainly used in processor chips for mobile devices. In addition, high-density FOWLP also has a large market in other processing chips, such as AI, machine learning, and the Internet of Things.

▼ TSV packaging—the leader in 3D IC packaging

TSV achieves vertical electrical connection throughout the thickness of the chip and opens up the shortest path between the upper and lower surfaces of the chip. TSV packaging has the advantages of better electrical interconnectivity, wider bandwidth, higher interconnect density, lower power consumption, smaller size and lighter weight.

Figure 19. TSV schematic diagram

Data source: IEEE, China Fortune Land Development Industry Research Institute

TSV, short for through silicon via technology, is a new technical solution for interconnecting stacked chips in 3D ICs: holes are drilled on the silicon wafer by etching or laser (the process can be divided into three types: first drilling, middle drilling, and last drilling), and then filled with conductive materials such as copper, polysilicon, tungsten and other substances.

Figure 20. TSV application scenario

Data source: Yole, China Fortune Land Development Industry Research Institute

TSV technology was first used in CMOS and MEMS, and is being promoted in FPGA, memory, sensors and other fields. In the future, it will also be used in optoelectronics and logic devices. 3D memory chip packaging and mobile phones will be the most widely used areas for TSV technology. According to Yole's forecast, the number of wafers using TSV technology will grow at a compound annual growth rate of 10% from 2016 to 2021.

Figure 21. TSV and 3DIC technology evolution path

Data source: Yole, China Fortune Land Development Industry Research Institute

▼ SiP packaging—system-level packaging breakthrough

Unlike the previous three technologies, SiP has achieved a breakthrough in semiconductor product packaging. SiP, or system-level packaging, is a packaging method that places different chips side by side or stacked. The stacked chips can be multiple active electronic components and passive devices with different functions, or MEMS or optical devices. After being packaged together, they become a standard package that can achieve certain functions, or form a system.

Figure 22. Schematic diagram of SiP system-level packaging

Data source: AMS, China Fortune Land Development Industry Research Institute

Figure 23. Moore's Law and Beyond Moore's Law

Data source: ITRS, China Fortune Land Development Industry Research Institute

Moore's Law is gradually slowing down, and the semiconductor industry is now entering the post-Moore era. ITRS pointed out that both SoC and SiP can achieve higher performance and lower cost for integrated circuits. SoC system-level chip is a chip-level product with highly integrated circuits with different functions in the chip. SiP not only maintains the advantages of core resources and semiconductor production processes, but also can effectively break through the limitations of SoC in the process of chip integration, overcome difficulties in SOC such as process compatibility, signal mixing, noise interference, electromagnetic interference, etc., greatly reduce the cost of design and manufacturing, and have the flexibility of customization.

Figure 24. Comparison between SiP and SOC

Data source: ITRS, China Fortune Land Development Industry Research Institute

SiP packaging is widely used, including wireless communications, automotive electronics, medical electronics, computers, military electronics, etc. SiP was first used in the field of wireless communications and is also the most widely used field.

Currently, smartphones are the largest market for SiP packaging. As smartphones become thinner and lighter, the demand for SiP continues to increase. For example, the iPhone 6s has greatly reduced the use of PCBs, and many chip components are built into SiP modules. In the iPhone X, the use of SiP packaging has reached an unprecedented level, including nearly 30 chips (RF and touch chips, etc.), including 18 filters. In addition, Apple Watch has been using SiP packaging from the first to the latest model.

Figure 25. SiP packaging components in iPhoneX

Data source: System Plus, China Fortune Land Development Industry Research Institute

In 2017, the world's top ten OSAT companies achieved revenue of approximately US$28.1 billion, a year-on-year increase of 15.3%, exceeding 50% of the global packaging and testing industry's revenue and accounting for more than 90% of the total revenue of OSAT companies. Among the world's top ten OSAT manufacturers, 5 are from Taiwan, 3 are from mainland China, 1 is from the United States, and 1 is from Singapore. Oligopoly is obvious, with the top three accounting for more than 60% of the market share. In recent years, the global semiconductor industry has been undergoing continuous mergers and acquisitions, mainly because the industry has entered a mature stage and competition has become increasingly fierce. Manufacturers have expanded their scale or made strategic arrangements for the future through mergers and acquisitions. The trend of the big getting bigger is becoming more and more obvious, and the packaging and testing industry is no exception.

Figure 26. Global OSAT company rankings in 2017

Data source: Company annual report, China Fortune Land Development Industry Research Institute

Figure 27. Global OSAT market share in 2017

Data source: Company annual report, China Fortune Land Development Industry Research Institute

Figure 28. Global OSAT enterprise mergers and acquisitions

Data source: Company announcement, China Fortune Land Development Industry Research Institute

The development speed of China's packaging and testing enterprises far exceeds the international level

In 2017, the top three OSAT companies in China (JCET, Huatian Technology, and Tongfu Microelectronics) achieved revenue of RMB 37.3 billion, a year-on-year increase of 27.7%, accounting for 19.7% of the total output value of China's packaging and testing industry. The revenue growth rate of domestic packaging companies is significantly faster than the global level, thanks to the expansion of traditional packaging capacity and the commissioning of some advanced packaging capacity, and has good development potential.

In 2017, the global market share of design, manufacturing and packaging and testing in the semiconductor industry of mainland China was 9%, 7% and 22% respectively, and the packaging and testing industry has obvious comparative advantages. Well-known IC design companies in Taiwan, such as MediaTek, Novatek and Realtek, have gradually shifted their packaging and testing orders to mainland counterparts.

Development opportunities for China's packaging and testing industry

Before 2010, there were less than 70 Chinese packaging and testing companies, of which less than 20 were local companies. In 2017, there were more than 100 Chinese packaging and testing companies, mainly located in the Yangtze River Delta (55%), the Pearl River Delta, the Bohai Rim and the western region. Among them, there are more than a dozen companies involved in advanced packaging business, of which about half are local companies. Almost all of the world's top IDMs and wafer fabs have factories in mainland China, with more than 20 from 2017 to 2020, far exceeding the number of other countries and regions. Newly built wafer fabs are expected to cooperate with excellent domestic packaging and testing companies, which will bring the first spring breeze to the development of China's semiconductor packaging and testing industry.

From the perspective of technological updates, the semiconductor manufacturing industry continues to develop in accordance with Moore's Law, continuously investing in new production lines to achieve capacity expansion and technological updates. From the figure below, we can see that following Moore's Law, wafer manufacturing has undergone nearly 20 rounds of technological updates, while the overall packaging technology has only undergone a few generations of technological changes during the same period. In the latest generation of technological changes, China's leading packaging and testing companies have quickly achieved synchronous development with the world's top companies through mergers and acquisitions. Compared with the wafer manufacturing industry, which is two generations behind, testing and sealing is undoubtedly the most internationally competitive industry link. Leading companies Changdian Technology and Huatian Technology both have the world's most cutting-edge advanced packaging technology. In recent years, the number of patent applications in China's packaging and testing industry has shown explosive growth. These are undoubtedly the source of the spring breeze for the development of China's packaging and testing industry.

Figure 29. Node comparison between semiconductor manufacturing and semiconductor packaging and testing

Data source: SIA, China Fortune Land Development Industry Research Institute

Figure 30. Comparison of advanced packaging technologies among China’s top three companies

Data source: Company announcement, China Fortune Land Development Industry Research Institute

Figure 31. Major countries/regions for semiconductor packaging and testing patent applications worldwide and their application trends

Data source: incopat, China Fortune Land Development Industry Research Institute

By the end of 2017, the first phase of the National Integrated Circuit Industry Fund had invested nearly 10 billion yuan in the test and packaging industry, with the top three local companies accounting for 70% of the total investment. Changdian Technology, Huatian Technology, and Tongfu Microelectronics were all major strategic project companies invested by the first phase of the big fund. It is understood that the second phase of the big fund's investment layout will shift from "coverage" to "point breakthrough", which will further benefit the leading companies to concentrate their efforts on breaking through high-end technologies. In addition to industrial investment, in September 2017, the increase in the pre-tax additional deduction ratio for corporate R&D expenses was also a spring breeze to encourage the development of the semiconductor industry, which accounts for a relatively large proportion of R&D.

To forge iron, one must be strong enough, and continue to increase research and development of advanced packaging technology

Changdian Technology, Huatian Technology, and Tongfu Microelectronics have all expanded their production capacity and increased their market share through acquisitions, and more importantly, they have improved their advanced packaging and testing capabilities. In terms of gross profit margin and net profit margin, these three companies are at a relatively low level, and they need to continue to improve their operating cost control and management expenses. In terms of R&D, although Chinese companies have a higher ratio, the total amount is small. The total R&D expenditure of the three companies is less than that of ASE alone. In the accumulation of advanced packaging technology, domestic companies need to continue to make breakthroughs.

Since the beginning of this year, the trend of overseas mergers and acquisitions by domestic capital has slowed down. The focus of China's packaging and testing industry should shift to the development of advanced packaging and testing technologies, increase R&D investment, and actively demonstrate its technical strength to the market through customer certification to maintain competitiveness. In addition, Chinese OSAT companies need to actively change their R&D model. At present, Chinese companies' R&D investment is mainly internal technology R&D, and their ability to jointly develop with customers is relatively weak. In the future, Chinese OSAT companies should actively develop with upstream customers to form higher profits and better bargaining power in the early stage of mass production, which will also help maintain a sustained profit advantage.

References:

1. Recent Advances and New Trends in Flip Chip Technology, John H. Lau, Journal of Electronic Packaging, Transactions of the ASME, Vol. 138, 2016

2.Wafer Level Packaging(WLP): Fan-in, Fan-out and Three-Dimensional Integration, Xuejun Fan, IEEE- Xplore, 2010

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