Large-scale SoC design faces challenges and the EDA industry is experiencing new changes

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As the new generation of 4G smartphones and connected devices move towards multi-core design, the system-on-chip (SoC) provides a wider design space with the support of the new generation of wafer fab process, allowing the design engineering team to integrate the silicon intellectual property (IP) of various modules such as different digital/analog circuits into a single chip according to different product requirements, making it have more complex and more complete system functions.

SoC has become the mainstream trend in the chip design industry, and product value and competitiveness depend entirely on complexity, design reusability, and process yield.

Today, IC design engineering teams rarely start from scratch when participating in new SoC project designs. Most of them are based on a combination of different proven legacy design modules and various IP blocks. Especially considering the design schedule of a new SoC chip, under the pressure of product launch time, the engineering design time is greatly compressed. When IC design engineers begin to race against time, EDA tools are also required to keep pace with the times, and existing traditional IC design tools are also brewing a new wave of changes.

Dr. Ajoy Bose, founder and CEO of Atrenta, was interviewed about the challenges currently faced by large-scale SoC designs, and how Atrenta's EDA front-end design software tools can help customers solve problems and bring competitive advantages.

Atrenta makes its debut with EDA tool for RTL design verification

Atrenta is a design software tool provider for EDA front-ends located in Silicon Valley, California. The founder, Dr. Bose, has been devoted to the research and development of EDA technology since he was at the University of Texas at Austin in the 1970s. He then joined AT&T Bell Labs to develop the earliest EDA tools. In the following years, due to mergers and acquisitions between different EDA companies, he joined major EDA companies such as Cadence, completing his training and growth as an EDA engineer. It can be said that he has been in the field of EDA technology and industry all his life.

When Atrenta was first founded, it was all for a special product idea. In 2001, it took on a special commissioned project from Intel to help IC design engineers by checking RTL designs, so that they could discover and solve problems in the early stages of design. For the company, this could meet the needs of shortening chip design and time to market, and the cost and benefit of solving problems at this time was the highest.

This success made Atrenta's EDA tools debut in the market, and the idea of ​​starting a business was born. The goal is to help IC design companies face new changes and challenges more efficiently, especially to create a new situation for Atrenta in the competitive game dominated by the top three EDA giants. Currently, more than 250 companies and thousands of design and verification engineers around the world rely on Atrenta's products to reduce design risks, reduce costs, and improve verification efficiency.

SpyGlass, GenSys and BugScope usher in a new era of EDA tools

The integration trend of cutting-edge technologies triggered by SoC today is a good example. In the current new generation of large SoC, there are more than hundreds of millions of logic gates, integrating a variety of different IPs, and reusing proven design modules to a large extent. The number of different clocks used can reach dozens or even hundreds. The functions and complexity of the products are no longer the same as the previous generation.

As the scale of complexity exceeds that of the past, wafer fab processes are moving towards 16 and 14 nanometers, and SoC designs are importing a large amount of IP. Even if these individual IP modules are proven designs, the interaction between these different IPs when combined together is an important issue that the IC design team needs to face, and it also creates new impacts and challenges for EDA tool manufacturers.

In the face of engineering challenges and considerations that are very different from the past, the role played by EDA tools must be able to more actively help engineering teams discover and solve problems in the early stages of design. In response to the soaring complexity of SoC design, Atrenta has launched a series of solutions to increase the efficiency of IC design. For example, using the SpyGlass series of products to perform static verification and formal checking for RTL, supplemented by GenSys' automatic reorganization of RTL to make IP combinations, and BugScope's dynamic simulation verification tools to improve verification coverage to face severe challenges.

SpyGlass, Gensys and BugScope constitute Atrenta's three major product lines, allowing users to achieve complete design integration. Atrenta uses these EDA tools to help IC design engineers reduce the number of repeated design modifications, thereby completing high-quality SoC design solutions, which has been proven to be a set of tools with significant results in the market.

As SoCs become larger and larger, different functions are continuously integrated on one SoC. It is inevitable that various functional modules must be connected and verified. Therefore, Atrenta has developed a series of SpyGlass tool suites to discover and solve problems in the early stages of design. Its solutions cover LINT (syntax checking), DFT (design testability), CDC (cross-clock domain crosstalk), SDC Constraint verification, Power (power consumption) estimation, optimization, verification and design sign-off, etc., to ensure accurate and functionally complete RTL inspection, as well as IP verification, and enhance its SoC design and verification process.

Design engineers can discover and identify potential design problems and correct them during the RTL stage, so that the later stage design operations can be efficient and improve productivity.

SpyGlass is Atrenta's earliest product line. It has accumulated many years of practical experience. The product line is relatively diverse and rich. It currently contributes 80% of the revenue. In terms of regions, the Asia-Pacific region, including Japan, has expanded rapidly in the past one or two years and has expanded to more than 40% of the revenue source.

BugScope is a relatively new product line that Atrenta created through acquisitions a few years ago. Although the product is new, it has great market potential. Unlike SpyGlass, which uses static detection, it uses dynamic simulation signals to test and verify different SoC functions. It is a very good complement, allowing users to fully verify and consider various configurations and conditions.

Multinational IC design company uses EDA tools to integrate different design teams

Atrenta announced a few months ago that it has won the adoption of Atrenta products by MediaTek, a leading customer in Taiwan, which once again demonstrated the value of SpyGlass tools and affirmed Atrenta's strength. Atrenta currently has more than 250 customers worldwide, including most of the top IC design and well-known consumer product multinational companies.

According to Dr. Bose's observation, today's multinational IC design companies, due to the high degree of internationalization of talents and the trend of large-scale SoC design projects, face such a high-complexity technical challenge. The consistency of EDA tools and design specifications used by design teams is very important. SpyGlass has become a verification tool that provides analysis tools and design specifications. The core design team can use this series of tools to evaluate and communicate with other remote design teams.

For EDA companies, being able to cooperate with large multinational customers means not only good reputation and customer recognition, but more importantly, the success of product marketing strategies.

The platform-based EDA tool era leads the fifth EDA industry revolution

In the past 60 years of semiconductor industry development, EDA tool development has a history of 50 years. From the earliest CAE tools in the 1980s, to the focus on providing DesignFlow in the 1990s, and then EDA tools gradually split into Front-End and Back-End development, and after 2000, the focus was on manufacturability solutions.

Dr. Bose believes that the upcoming fifth EDA industry revolution, that is, the platform-based design EDA tool generation, requires a very comprehensive platform and overall approach to assist, such as expanding DesignFlow, integrating various single-point tools, IP, design and process, and using the same EDA tool platform to reduce the cost of SoC chip or IP integration and verification, thereby reducing the overall SoC development schedule and cost, etc. These are Atrenta's product strategy and development direction.

Currently, platform-based EDA tools have become the focus of the top three EDA manufacturers. Atrenta's technical team also has close cooperation with the top three EDA manufacturers. This good competitive and cooperative relationship can allow the EDA industry to have a larger market and benefit everyone.

Dr. Bose's observations on Taiwan's IC design companies show that although Taiwan's current achievements in semiconductor manufacturing have been widely praised by the industry and it has become the world's leading IC manufacturing ecosystem, the scale of its IC design industry is relatively conservative in comparison.

Currently, a few Taiwanese IC design companies with foresight and market value have begun to emerge on the world IC design stage. In particular, the vitality and progress shown by many young and outstanding Taiwanese engineers are indeed impressive, and the Taiwanese IC design community is growing stronger and stronger. Atrenta has always maintained a close cooperation strategy with important customers, and usually first understands the chip development trend of the entire industry in the next one to one and a half years, which will be very helpful to the booming Taiwanese IC design industry. Atrenta hopes to grow and thrive with the Taiwanese IC design industry to create a win-win opportunity.

Source: Sina Technology

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