Inventory of those classic IC packaging types

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Editor's note: This is an old article on the Internet, which reviews some of the packaging technologies that are now widely used. I hope it can be helpful. If there are any mistakes, please point them out. In addition, if you think there are any packaging technologies that have appeared and will become mainstream in the future, please leave a message to discuss. Thank you!

Everyone is already familiar with CPUs . I believe you can name the features of various CPU models. However, when it comes to the packaging of CPUs and other large-scale integrated circuits, few people are really familiar with them. The so-called packaging refers to the shell used to install semiconductor integrated circuit chips. It not only plays the role of placing, fixing, sealing, protecting chips and enhancing electrical performance, but also serves as a bridge between the internal world of the chip and the external circuit. The chip is connected to the pins of the package shell through wires, and these pins are connected to other devices through wires on the printed circuit board. Therefore, packaging plays an important role for integrated circuits.

As mankind has entered the 21st century, it can be said that the future development of the world is based on the electronics industry, and the foundation of the electronics industry is IC manufacturing technology. The purpose of chip packaging technology is to give IC chips a set of organizational structures so that they can function stably. In terms of the entire chip manufacturing process, chip packaging technology belongs to the manufacturing technology of the second half of the product, so packaging technology is often considered to be just one of the supporting roles of chip circuit manufacturing technology. In fact, the scope of packaging technology covers a wide range. It applies knowledge of physics, chemistry, mechanics, materials, electromechanics, etc., and also uses a variety of materials such as metals, ceramics, and polymers. In the field of microelectronics, the functional requirements for chips are getting higher and higher, and the environment in which chips are used is becoming more and more demanding. The importance of developing chip packaging technology is no less than that of chip manufacturing technology and other microelectronics-related technologies. Therefore, major microelectronics companies in the world are competing to develop a new generation of packaging methods in order to gain technological leadership.

The main production process of packaging includes: Wafer cutting, cutting and separating each die on the wafer. Die-Attach , placing the cut die on the lead frame. Wire Bond , connecting the die signal contact to the lead frame with metal wires. Sealing, isolating the die from the outside world. Inspection / molding, removing the excess residual glue after sealing, and inspecting and molding the IC on the lead frame. Printing, printing the model, production date, batch number and other information on the surface of the IC . Inspection, testing the quality of chip products.

The position of packaging in the IC manufacturing process

How to measure whether a chip packaging technology is advanced? First, we need to look at the ratio of chip area to package area. The closer this ratio is to 1 , the better. Of course, this ratio can never be equal to 1 , and it should be called "bare crystal". For example, taking a CPU with a 40 -pin plastic dual in-line package (P DIP ) , its chip area / package area = 3 × 3/15.24 × 50 = 1:86, which is far from 1. It is not difficult to see that this package size is much larger than the chip, indicating that the packaging efficiency is very low and occupies a lot of effective installation area. Next, we need to look at the pin design. In theory, the pins should be as short as possible to reduce signal delay; the distance between pins should be as far as possible to ensure that they do not interfere with each other. However, as the number of transistors integrated becomes larger and larger, more and more additional functions are added to a single chip. The number of pins is increasing day by day, and the spacing between them is getting smaller and smaller. The number of pins has gradually increased from dozens to hundreds, and may reach 2,000 in the next five years . Based on the requirements of heat dissipation, the thinner the package, the better. As the integration of chips increases, the heat generated by chips is also increasing. In addition to adopting more sophisticated chip manufacturing processes, the quality of package design is also a crucial factor. Designing an excellent package can greatly increase the various electrical properties of the chip. Such as relatively small impedance value, strong anti-interference ability, small signal distortion , etc.

The chip packaging technology has gone through several generations of changes, from DIP , QFP , PGA , BGA to CSP and then to MCM . The technical indicators and electrical performance are more advanced than the previous generation. The following will introduce the various chip packaging technologies.

DIP package

In the 1970s , dual in-line packages were popular. DIP (Dual In - line PAC kage) refers to integrated circuit chips packaged in dual in-line form. Most small and medium-sized integrated circuits use this package, and the number of pins generally does not exceed 100. It is the packaging method used by Intel 8 -bit and 16 -bit processing chips. Cache chips, BIOS chips and early memory chips also use this packaging method. Its pins are led out from both ends and need to be inserted into a dedicated DIP chip socket. Of course, it can also be directly soldered on a circuit board with the same number of solder holes and geometric arrangement . When inserting and removing the DIP packaged chip from the socket, special care should be taken to avoid damaging the pins. Later derived DIP package structures include: multi-layer ceramic dual in-line DIP , single-layer ceramic dual in-line DIP , lead frame DIP . The packaging materials are also diverse, including glass ceramic packaging, plastic package packaging, ceramic low-melting glass packaging, etc. DIP package is suitable for welding on the early single-layer PCB circuit board, and adopts the through-hole welding method, which is convenient for welding. However, due to the large ratio between the chip area and the package area, the volume is also large and the heat is also high.

The BIOS chip on the motherboard is packaged in DIP

Chip Carrier Package

Chip carrier packaging appeared in the 1980s. The packaging forms of these carriers include: wireless ceramic chip carrier LCC C (Leadless Ceram ICChip Carrier) , plastic quad flat package P QFP (Plastic Quad Flat PAC kage) , small size package SOP (Small Outline Package) , and plastic wired chip carrier PLCC (Plastic Leaded Chip Carrier) .

P QFP is the most common packaging form. The distance between its chip pins is very small, and the pins are very thin. Many large-scale or super-large integrated circuits use this packaging form, and the number of pins is generally more than 100. The 80286 , 80386 and some 486 motherboard chips in the Intel series CPU use this packaging form. Chips in this packaging form must use SMT technology (surface mount equipment) to weld the chip to the circuit board . Chips installed using SMT technology do not need to be punched on the circuit board. Generally, there are designed solder joints for the corresponding pins on the surface of the circuit board. Align the pins of the chip with the corresponding solder joints to achieve welding with the motherboard. Chips welded in this way are difficult to remove without special tools. SMT technology is also widely used in the field of chip welding. Since then, many advanced packaging technologies have required SMT welding.

The following is an AMD 286 processor chip in a QFP package . 0.5mm solder center distance, 208 I/O pins , 28 × 28mm overall dimensions, 10 × 10mm chip size , then chip area / package area = 10 × 10/28 × 28 = 1:7.8 , which shows that the QFP package size is much smaller than that of the DIP .

P QFP packaged motherboard sound card chip

Schematic diagram of a chip with 44 pins in QFP package

SOP has a variable number of pins and a flexible and compact size. On its basis, a thinner TSOP (Thin Small Outline PAC kage) packaging technology has been developed. However, because the distance between the pins of this package is only 1.27 , 1.0 , and 0.8mm . Therefore, it is not possible to integrate too many pins, generally between 8 and 48. Therefore, TSOP has become the most popular memory packaging form. A typical feature of TSOP memory packaging technology is to make pins around the packaged chip, such as two rows of pins on each side of the SDRAM memory module, and pins on all four sides of the SGRAM memory module. TSOP is suitable for installing wiring on PCB circuit boards using SMT technology . When the TSOP package size is reduced, the parasitic parameters will be reduced accordingly ( electrical parameters that cause output voltage disturbances when the current changes greatly ) , which is suitable for high-frequency applications, and the packaging operation is relatively convenient and the reliability is relatively high. The subsequently improved and derived TSOP technology is currently widely used in the manufacture of SDRAM memory, and many well-known memory manufacturers are currently using this technology for memory packaging.

SOP package , 28- pin chip

PLCC package is also quite common. This package is square, 32-pin package, with pins all around, and its size is much smaller than DIP package. PLCC package is suitable for installation and wiring on PCB using SMT surface mounting technology , and has the advantages of small size and high reliability. Most motherboard BIOS now adopt this package.

PLCC packaged motherboard BIOS chip

PLCC package diagram

PGA Package

With the rapid development of the semiconductor industry, the number of pins required has continued to increase. The old model of peripheral arrangement of leads cannot solve the problem of increasing pins even if the lead spacing is further reduced. Therefore, a new concept of area array arrangement was proposed. Array packaging was born.

The PGA (Pin Grid Array PAC kage) chip packaging format has multiple square-shaped pins inside and outside the chip, and each square-shaped pin is arranged at a certain distance around the chip. Depending on the number of pins, 2-5 circles of pins are arranged around the chip as the center. When installing, insert the chip into a dedicated PGA socket. In order to make it easier to install and remove the CPU , a ZIF CPU socket appeared starting with the 486 chip, which is specifically used to meet the requirements of PGA packaged CPUs in installation and removal.

ZIF (Zero Insertion Force Socket) is a socket that is unique to socket -structured CPUs . By opening and closing the lever next to the socket, the resistance of the socket to the pins can be adjusted, thereby firmly locking the CPU . Even if the CPU is replaced many times , it will not cause wear. The emergence of the ZIF socket solves the big problem of CPU upgrades in the future. As long as the chipset of the user's motherboard supports it, it can be upgraded to a faster CPU .

PGA packaging has had an advantage in high-density packaging for many years, and most of its products are used in computers with high pin counts, high power, and high performance. The number of pins is generally between 100 and 500. In the Intel series CPU , 80486 , Pentium , and Pentium Pro all use this packaging form. Of course, many packaging forms have been derived based on PGA . CPGA ( Ceram IC Pin Grid Arrau PAC kage ceramic pin grid array package) is suitable for Intel Pentium MMX , AMD K6 , AMD K6-2 , AMD K6 Ⅲ, VIA Cxrix Ⅲ, Cxrix/IBM 6x86MX , IDT Win Chip C6 and IDT WinChip 2 processors. PPGA (Plastic PinGrid Aoray Package ) is suitable for the packaging of Intel Celeron processors (Socket 370) .

There is also the FC- PGA ( flip chip pin grid array ) package used by the Coppermine core Pentium 3 and Celeron 2 , and the FC-PGA2 package used by the new Tualatin core Pentium 3 and Celeron 3. The main difference between the two is that the latter has an additional metal cover on the top. This is because users reported that the core of the early Pentium 3 was very fragile. The huge heat sink could easily crush the core. The prefix FC refers to the use of different connection materials and methods to complete the circuit connection with the chip facing down, and the pins are led out from the bottom and form a regular array. This can integrate more pins, reduce electronic delays, reduce circuit board size, reduce packaging costs, and have higher yield strength and higher reliability.

Differences between FC- PGA and FC-PGA2 packages

SEC Packaging

In 1997 , with the release of Pentium 2 , Intel also brought a new generation of Slot 1 interface technology. However, the CPU packaging process that supports this interface is complex and the cost is extremely high. The CPU of Slot X architecture no longer uses ceramic packaging, but uses a printed circuit board with a metal shell. The processor components are integrated on the printed circuit board. Due to the backward production process at that time, the L2 cache circuit of the processor could not be integrated inside the processor under the 0.35 micron process. So the PII processor based on the Slot 1 interface we see has two large L2 cache chips on both sides of the circuit board. Since then, with the maturity of the 0.25 micron process, L2 can be integrated into the processor. Therefore, shortly after the launch of the Pentium 3 processor, the Socket interface processor was fully restored. At the same time, AMD also launched a similar Slot A interface in order to compete with Intel for the market . From the appearance, Slot 1 and Slot A are not much different, and the directions of the two on the motherboard are exactly opposite.

The old PII has two large L2 cache chips on both sides of the CPU core.

This type of package shell is called SEC (Single Edge contact Cartridge). SEC cards are designed to be inserted into Slot X slots, and their size is equivalent to that of an ISA slot. All Slot X motherboards have a fixture consisting of two plastic brackets, and the SEC card can be inserted into the Slot X slot from between the two plastic brackets . Among them, Intel Celeron processors use SEPP (Single Edge Processor PAC kage) single-edge processor packaging; Pentium Ⅱ uses SE CC (Single Edge Contact Connector) single-edge contact connection packaging; Intel 's Pentium Ⅲ uses SECC2 packaging. AMD 's K7 Athlon processor based on the Slot A interface also uses SEC packaging.

BGA Package

In the 1990s , with the advancement of integrated circuit technology, the improvement of equipment and the use of submicron technology, LSI , VLSI and ULSI appeared one after another, the integration of silicon chips continued to increase, and the requirements for integrated circuit packaging became more stringent. The number of I/O pins increased sharply, and power consumption also increased accordingly. In order to meet the needs of development, a new ball grid array package, referred to as BGA (Ball Grid Array PAC kage) , was added on the basis of the original packaging form . It is considered to be the third generation of area array IC packaging technology. It arranges many solder balls in an array at the bottom of the crystal grain, and uses these solder balls to replace the traditional lead frame. Each solder ball is a pin. The solder balls are regularly arranged at the bottom of the chip, forming this unique packaging structure.

Solder balls used in packaging

As soon as BGA appeared, it became the best choice for high-density, high-performance, multi-functional and high- I/O pin packaging of ultra-large-scale chips such as CPUs , north and south bridges. Many semiconductor companies generally use this highly integrated packaging form, and a single chip can integrate more than 3 million transistors . Many CPU chips with high power consumption, such as Pentium , Pentium Pro , Pentium Ⅱ and i850 chipsets, all use ceramic pin grid array packaging CPGA and ceramic ball grid array packaging CBGA ( Ceramic BGA ) . And Intel began to install micro fan heat sinks on the chip to make the circuit work stably and reliably.

The world's first BGA packaged motherboard chipset i850

Ball grid array packaging technology has many benefits that are rare in traditional packaging processes. It can provide more pins in a smaller area, produce a strong "ball" structure, and integrate seamlessly into the manufacturing process. Its package area is only about 1.5 times the chip area. Compared with PLCC or P QFP packages, BGA packages significantly save circuit board area. For example, the new 49- ball CBGA package saves almost 84% of circuit board area when compared with the standard 44 -pin PLCC . BGA packaging technology has a variety of options including : 49 , 100 , 144 , 208 , 256 , 272 , 388 , 484 , 492 , 676 balls. The reduction in package size and height saves up to 84% of printed circuit board space . BGA packages have better device noise characteristics and power management characteristics.

BGA can make the chip smaller

Another major advantage of BGA is its high yield rate. Companies such as Motorola and Compaq claim that there are basically no defects in their 0.05- inch pitch packages with 160 to 225 I/O leads . In other fully automated factories, the failure rate of fine-pitch devices with the same number of I/O leads is 500 or 1000 PPM . Currently, the mainstream BGA package has 400 to 700 I/O leads , and Japan has even reported the research and development results of BGA packages with 2000 I /O leads .

With the gradual popularity of Intel BX motherboards and Super7 structure motherboards, 100 MHz external frequency has occupied the dominant position in the market. In order to better cooperate with it, memory products have also been introduced one after another. Intel 's PC-100 memory standard came into being in such a big environment. According to Intel's official documents, the clock frequency of the memory is 100 MHz and the reading speed must reach 167 MHz . However, traditional memory ICs use TSOP packaging. After exceeding 150 MHz , there will be great signal interference and electromagnetic interference. Therefore, for PC-100 memory packaged in TSOP , it is already somewhat incapable at 100 MHz external frequency, not to mention the PC-133 standard that is about to be released . After that, Taiwan manufacturer KINGMAX released Tiny - BGA packaging technology in August 1998. In fact, Tiny-BGA technology can be regarded as an ultra-small BGA architecture. The use of Tiny -BGA packaging will be smaller, only about 1.2 times. It greatly enhances the efficiency of PC-100 , provides better heat dissipation coefficient, and significantly reduces the impact of electromagnetic waves. Soon after its release, the finished product was officially launched on the market, replacing the traditional TSOP technology and becoming the "newcomer" in memory. It is used in many high-end display cards. Most of the subsequent DDR and DDRII memories also use Tiny-BGA packaging.

kingmax latest colorful Tiny- BGA package 256MB DDR 400 memory

μBGA (MICro Ball Grid Arrax) micro ball grid array package. μBGA package is an improvement on BGA . According to the 0.5mm solder area center distance, the ratio of chip area to package area is greater than 1 : 1.14 . The finished memory stick has a solid metal shell outside the package, which is quite good in anti-interference ability. It is an exclusive patent of Tessera , especially suitable for DRDRAM working in high frequency state , but the manufacturing cost is extremely high. It is currently mainly used in Rambus memory.

Rambus memory without the outer metal shell

CSP package

At the same time as BGA technology began to be promoted, another CSP packaging technology developed from BGA began to emerge. This is the legendary CSP packaging form. Its full name is Chip Scale PAC kage , which means chip-level packaging. As a new generation of chip packaging technology, on the basis of BGA and TSOP , the performance of CSP has been revolutionary improved. CSP packaging can make the ratio of chip area to packaging area exceed 1 : 1.14 . It is very close to the ideal situation of 1:1 . Compared with BGA packaging in the same space, CSP packaging can increase the storage capacity by three times. Its absolute size is only 32 square millimeters, which is equivalent to 1/6 of the TSOP packaging area . In the same volume, the memory module can be loaded with more chips, thereby increasing the single capacity. CSP packaging is also very thin, and the most effective heat dissipation path from the metal substrate to the heat sink is only 0.2mm . Under the same chip area, the number of pins that CSP can achieve is obviously much more than that of TSOP and BGA . TSOP has a maximum of 304 pins, BGA can reach a limit of 600 pins, and CSP can theoretically reach 1,000 pins. Due to such a highly integrated feature, the distance from the chip to the pin is greatly shortened, the impedance of the line is significantly reduced, and the attenuation and interference of the signal are greatly reduced. This also makes the access time of CSP 15%~20% better than that of BGA .

The earliest CSP packaged memory on the market is the so-called tCSP package ( thin chip scale PAC kaging ) launched by Jinbang Technology . It has fast data transmission speed, high capacity expansion, good heat dissipation and durability. The chip using tCSP packaging technology is small in size, only half of the TSOP packaged chip, so it can insert twice as many chips as TSOP on the same unit area of ​​the baseboard , thereby increasing the memory capacity. At present, the memory capacity of SDRAM using tCSP can be as high as 1GB . Due to the small size of tCSP memory, its application has been greatly increased, especially for products with limited memory installation space such as laptops. The unique structure of tCSP significantly improves its conductivity and convection, thereby improving the heat dissipation capacity of the chip. With such advanced packaging, Jinbang successfully launched the world's first DDR433 memory in June 2002 .

t CSP packaged DDR433 memory module

Subsequently, Kingston released its patented EPOC (Elevated PAC kage Over CSP ) three-dimensional memory module double-layer packaging technology. It looks more like a combination of TSOP and CSP , with the top TSOP packaged chip encapsulating the lower ultra-small CSP packaged chip. There is no chipset interconnection technology or physical contact between the two chips, and it is not a true MCM package. Air is allowed to pass between the top and bottom chips, which effectively improves the heat dissipation efficiency. Since EPOC can integrate more memory particles on the same circuit board, it is a new packaging technology for the future, which effectively controls the price of server memory and improves the performance-price ratio of high-capacity modules. It also gives a lot of inspiration to other packaging designers, and the combination of three-dimensional packaging module technology and multiple packaging methods has opened a new page.

Internal CSP packaged chip

EPOC plan view

MCM package

After looking at the various packaging technologies mentioned above, it is not difficult to see that a single form of packaging technology always has more or less defects. Using only one packaging technology cannot meet the needs of multiple fields. Therefore, multiple high-integration, high-performance, and high-reliability chips are combined into a variety of electronic module systems using SMT technology on a high-density multi-layer interconnect substrate, thus producing MCM (Multi Chip Model) multi-chip module packaging. The benefits of MCM are obvious. It can enable faster information transmission between internally packaged chips, reduce the size and weight of the chip, and make the chip more stable. However, the design and development process of MCM is relatively complicated, and the cost is relatively high.

For chips of the same size, MCM has a smaller size.

On the basis of MCM , 3D structure packaging has been developed , that is, multiple chips are stacked vertically to form a chipset, and then packaged. In this way, the various electrical properties of the chip can be improved, making the chip more powerful. The key is the connection of the wire. The industry usually calls the line width less than 100 microns fine line (very fine) . Now the minimum line width can be between 50 and 35 microns, which can meet the needs of the present and the future. "Ultrafine" refers to a line width of less than 15 microns. This line width can meet the requirements of connecting flip chips in precision pitch arrays in the next few years. At present, many large semiconductor companies such as IBM and SUN are developing "very fine line" and "ultrafine line" processes based on low-cost materials to meet the needs of the next generation of ultra-large-scale integrated circuits and other applications.

Thin wires connect multiple layers of chips

BBUL package

Seeing this, we have to ask how the processors will be packaged in the future? The answer is: BBUL ( Bump less Build-Up Layer ) built-in non-bump layer packaging. It is the processor packaging technology that Intel will promote in the next few years. It was originally proposed by Intel's ATD ( Assembly Technology Development). Although this technology has not been needed for 5-6 years, it has indeed changed the traditional packaging concept. Although AMD 's processors surpass Intel 's chips in terms of instruction execution efficiency and chip performance, they are far less advanced than Intel in manufacturing process research and development and application . Intel even has an independent department engaged in the research and development of packaging technology, with more than 900 employees working there , and invests considerable research and development funds every year to study and test new packaging technologies. (Now you know why P4 is more expensive than Athlon ) Intel has the ability to integrate 1 billion transistors in the processor and increase the operating frequency to more than 10G Hz .

Internal structure of BBUL package

BBUL integrates the silicon chip into the core. Only a single-layer package is needed to manufacture the CPU , and the silicon chip is embedded in the package. BBUL does not require more solder joints. The silicon chip is directly embedded in the circuit board, and the thickness of the core will not be higher than the surface of the package. In addition, the heat-stretching protective metal greatly reduces the possibility of damage caused by incorrect installation. It allows the silicon chip to be more in contact with the capacitor at the bottom of the CPU , increases the signal transmission efficiency, and greatly reduces the physical volume. The core chip used in the BBUL chip is similar to the 0.13- micron Northwood , but the volume of the two is very different. The biggest advantage of BBUL is that similar to the MCM package, multiple processor cores can be integrated in a single chip, and the internal high-speed interconnection is much faster than the external bus. This design will greatly promote future multi-core processors.

Compared with the P4 package, it is much thinner and lighter.

Summarize

After spitting so much, I finally finished talking about the packaging technology I know. From this small packaging technology, we can taste how difficult and tortuous the development of semiconductors is. Look at the computers and mobile phones around you, those large and small colorful chips are the crystallization of the hard work of generations of industry elites! I believe that everyone who enjoys modern computer technology will have a different understanding of the computer in front of them. Maybe we may not be able to make much contribution to the development of science and technology in the future, but we should express our deep respect for those who have made contributions.

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