Chinese Academy of Sciences releases domestic open source RISC-V processor "Xiangshan": the first version is scheduled to be taped out in July

eric_wang

Chinese Academy of Sciences releases domestic open source RISC-V processor "Xiangshan": the first version is scheduled to be taped out in July [Copy link]

On June 23, the first RISC-V China Summit was held at ShanghaiTech University this week. At this conference, Bao Yungang, a professor at the University of Chinese Academy of Sciences and a researcher at the Institute of Computing Technology of the Chinese Academy of Sciences, released the domestic open source high-performance RISC-V processor core, Xiangshan. He said that there is currently no open source mainline like Linux in the CPU field, so the R&D team believes that the industry needs an open source high-performance RISC-V core that can be widely used by the industry and support the academic community to experiment with innovative ideas. The goal is to survive for at least 30 years like Linux.

With the support of the Institute of Computing Technology of the Chinese Academy of Sciences and Pengcheng Laboratory, Xiangshan has developed an open source high-performance RISC-V processor core together with industry companies through the China Open Instruction System (RISC-V) Alliance. The first mass-produced version "Yanqi Lake" is scheduled to be taped out in July this year, using TSMC's 28nm process.

Bao Yungang said that the project took more than a year of preparation, team building and funding application. On June 11, 2020, Xiangshan established a code repository on GitHub. In one year, 25 students and teachers participated in the development of Xiangshan, submitted 3,296 codes, with a total of more than 50,000 lines and more than 400 documents.

Xiangshan is an open source RISC-V processor core, and its architecture code is named after the lake. The first version of the architecture code is "Yanqi Lake". The RTL code of this processor was completed in April 2021, and it is scheduled to be taped out in July based on TSMC 28nm process. The current frequency is 1.3GHz.

The second version of the architecture is codenamed "Nanhu", which pays tribute to the 100th anniversary of the founding of the Communist Party of China. "Nanhu" is scheduled to be taped out at the end of this year, using SMIC's 14nm process and a target frequency of 2GHz.

Specifically, the "Yanqi Lake" architecture is an out-of-order processor core with 11 pipelines, 6 issues, and 4 memory access units. The issue width is comparable to some ARM high-end processor cores, but it has not been fully optimized, so there is still a big gap in actual performance. Professor Bao Yungang's team hopes that through continuous iterative optimization ("Nanhu"-->"X Lake"-->"Y Lake"-->...) in the future, the performance will reach the level of ARM A76.

In 2020, the team completed the test tape-out of an 8-core labeled RISC-V processor based on Chisel, using TSMC's 28nm process. The R&D staff built a streamlined automatic regression testing framework based on GitHub CI. Since September 2020, this test chip has successfully started the Linux/Debian system on the FPGA.

One of the important decisions in the development of the "Xiangshan" processor core was the selection of the agile design language Chisel. The reason is that the development efficiency is much higher than Verilog. To achieve the same function, the amount of Chisel code is only 1/5 of that of Verilog.

Another important decision during the development of Xiangshan was to attach great importance to building processes and tools that support agile design. This provided a scientific process for chip development and ensured the success rate. In addition, the R&D team also developed more than ten unique tools to support this agile design process.

IT Home learned that Xiangshan is currently developing the next-generation architecture "Nanhu", with the goal of tape-out by the end of this year. It is based on SMIC's 14nm process, has a frequency of 2GHz, a SPECCPU score of 10 points/GHz, supports dual-channel DDR memory and PCIe, USB, HDMI and more functions.

Officials said that the research and development of the Xiangshan processor core was supported by the Beijing Zhiyuan Artificial Intelligence Research Institute and senior experts from Beijing Microcore. In the second phase, it will also work with partners such as ByteDance, ESWIN, and USilicon Technology to jointly develop it.

minihang

Come and study

chunyang

RISC-V is the direction that can bridge the gap between teaching and industry.

wsmysyn

A former colleague of mine was an intern at the Institute of Computing Technology in 2015. At that time, he heard that RISC-v had been launched and several people were researching it, but he did not participate. After so many years, it is finally going to be taped out. . .

freebsder

The name Xiangshan is too uncreative and has none of the flavor of Hongmeng.

led2015

The more products we develop, the more technologies we need to learn