SiP advanced packaging is expected to develop into multiple new markets

Source: Content from Yole Electronics Industry News ， Thanks.

The semiconductor industry is moving towards continued size reduction and increased complexity, a trend that also drives the wider adoption of system-level packaging (SiP) technology.

One of the great advantages of SiP is that it can squeeze more functions into smaller and smaller chips, suitable for applications such as wearable devices and medical implants. Therefore, although the individual chips in the package have fewer functions integrated on a single die, the package as a whole has more functions in a smaller footprint. In fact, it is a complete electronic system in a single package, with the ICs arranged in a flat arrangement, vertical stacking, or a combination of both.

In addition, SiP technology is an extension of technologies that have been around for many years. It is based on existing packaging technologies such as flip chip, wafer bumping, wire bonding and fan-out wafer-level packaging.

Multi-chip modules (MCMs) are the predecessor of system-level packaging. MCMs were originally developed for data storage, such as bubble memory in the 1960s and 1970s, and for specific military/aerospace electronics. They are still used in certain products, such as Nintendo's Wii U game console. However, the adoption of this packaging solution is limited by the continuous evolution of Moore's Law, and current technology has made it easier to put all components on a single chip at a lower cost.

Fig. 1: TI bubble memory module Source: Chipsetc.com

This all started to change at the 16/14nm node, when continued shrinking of components became a challenge. The difficulty of manufacturing continues to increase after each new node due to a variety of factors. For example, at the 5nm node, it is expected that a completely new transistor structure will be introduced, and new materials such as cobalt or ruthenium will begin to be considered as replacements for copper in the interconnect structure. In addition, dynamic power density and self-heating issues have become challenges even at the 16/14nm node, and more attention and more advanced power management circuits will be required at 10nm and above. On the design side, routing congestion has been a growing problem, exacerbated by RC delays, electromigration, and physical effects such as heat, electrostatic discharge, and electromagnetic interference.

Advanced packaging technology offers some alternative approaches to these problems. First, it provides a way to minimize physical effects by using physical separation. For example, an analog block that is sensitive to digital noise or thermal effects can more easily mitigate the effects by using another independent chip. Second, because entire chips or chiplets can be reused in a package, it also makes it easier to reuse IP. Third, it can improve performance and reduce power consumption by increasing the diameter of the connectors between chips and shortening the distance signals must travel, thereby reducing the power required to drive those signals.

Yin Chang, vice president of sales and business development at ASE Group, said: "SiP is still in its infancy in terms of introduction. We are still exploring and learning all the possibilities of SiP. This is just the beginning of SiP."

However, advanced packaging has certainly moved beyond the basic research phase of exploring the feasibility and reliability of various packaging methods. The challenge now is to achieve the economies of scale of integrating everything on a single die, just as Moore's Law has. The semiconductor industry has developed a steady stream of options and technology developments to assist in this transition.

Chang said: "There are two levels of technological advancement. One is that in terms of 2.5D, the use of silicon interposers to connect various types of high-density silicon can maximize integration and promote performance in a small footprint. Secondly, in the past, combining various functions together would cause chips to conflict or interfere with each other. But the new technology can dynamically shield between these conflicting silicon and put them in a very small package, making it meet the small size application requirements mainly for wearable devices or IoT applications.

Fig. 2: SiP market relationship diagram Source: ASE

Other manufacturers are also working to improve the manufacturing process.

“The evolution of technology is primarily related to heterogeneous integration of multiple dies, and another key component – ​​efficient mix and match of passives on the smallest form factor,” said Urmi Ray, senior director at STATS ChipPAC. “This is a change that has occurred over the past few years, and the trend has been towards optimizing the key areas of passives and actives on very small form factors. In addition, we are also seeing very efficient handling, picking and placing of small, thin dies as well as the two larger components on the assembly side. The trend towards thinner dies is becoming more and more evident as form factor sizes shrink.”

Fig. 3: SiP moduleSource: STATS ChipPAC

Jean-Christophe Eloy, president and CEO of Yole Développement, made a similar observation. He noted that the design of Apple’s A10 processor, which is manufactured and assembled by TSMC, has allowed passive components to be moved into the chip design, rather than being considered as discrete components on a PCB. “Thanks to the A10 processor, which was developed by TSMC and Apple, integrated passive components are starting to be used in wireless mobile devices again,” he said.

Nozad Karim, vice president of SiP/system integration at Amkor Technology, opened last month’s System-in-Package (SiP) Technology Conference and Exhibition hosted by the International Microelectronics Assembly and Packaging Society (IMAPS) in Rohnert Park, California, with this question.

“There are many definitions of SiP,” he said. “It’s a system and it’s a package.”

Jan Vardaman, president of TechSearchInternational, added more details: "The industry needs to know clearly how we define SiP technology," she explained that SiP involves "two or more different dies" and "it forms a functional block." "SiP does not mean a single packaging method," Vardaman added. "Fan-out wafer-level packaging can also be considered SiP." But she pointed out that TSMC's InFO packaging technology does not meet the definition of SiP.

Vardaman estimates that SiP packaging shipments will reach 14.9 billion units in 2016. He believes that mobile devices, wearable devices and other consumer products account for about 82% of SiP use, and the market compound growth rate is estimated to be 13.7% from 2016 to 2020.

Vardaman noted that the iPhone 7 and 7 Plus smartphones each have about 15 SiPs, the Apple Watch Series 2 contains three SiPs, and the Samsung Galaxy S8 phone has 13 SiP packages.

As another reference point, Yole Développement predicts that by 2022, 4.5 million wafers (estimated on 12-inch wafers) will contain TSVs, which are used in interposers and other advanced packaging technologies.

Fig. 4: Advanced packaging growth forecast. Source: Yole Development

SiP applications are initially targeted at high-end networking, where network throughput is critical but price is not a key factor, as well as some consumer electronics and mobile markets, where initial development costs can be amortized over large demand and the overall price of the system.

Today’s main applications include integrating processors, memory, logic units and sensors into a single module, providing a one-stop solution for some customers. However, as costs decrease, these products are expected to be particularly useful for IoT device developers who need to quickly launch new products.

“The modularity of this solution allows us to quickly create solutions that can help reduce time to market,” said ASE’s Chang. “So we can use SiP for specific functions, allowing manufacturers to put it together very quickly and get the product out to the market. Especially for wearables and IoT, where the market is changing very quickly. These are two different needs that SiP can meet at the same time.”

SiP is also gradually penetrating into the automotive, industrial and medical electronics fields because of its ability to improve battery life in a smaller finished product size. SiP is also a suitable solution in applications with high performance requirements such as artificial intelligence and neural engines. Chang said: "SiP can be applied to a wide range of industries." The technology is also suitable for driverless vehicles, augmented reality, 5G wireless communications, etc.

Chang said: “We believe you can put it in an autonomous vehicle for the neural engine, where you want to integrate high-speed processing solutions into a very small form factor, so you don’t have to carry a huge computer on the car. You can do processing at high bandwidth, so you may need to use SiP to meet these high bandwidth needs, perhaps 5-, 6-, 7G transmission rates to the neural engine. In this regard, 2.5D solutions can provide heterogeneous silicon technology for these types of high-volume computing needs. In the augmented reality part, because you want to configure the display screen on the glasses, the size of the form factor will be key, and you will also want to maximize the battery life so that you don’t have to constantly charge the glasses to keep the AR running. So the ability to shrink the electronics and quickly modularize it to shorten the time to market will be key for these customers or companies. It is very interesting for us to develop products in these two areas with SiP. We can use all our experience in packaging and EMS to produce high-density modules and create solutions for AR manufacturers. Through our bumping wafer bumps, flip With our flip chip and redistribution technology RDL solutions, we can build a 2.5D neural engine for the next generation of driverless vehicles.”

STATS' Ray cited RF shielding and double-sided integration of active and passive components as two major advantages, which would allow the use of double-sided printed circuit boards in mobile phones, thereby reducing module size.

In terms of SiP adoption, Ray said "the modularization of functionality is a real market trend." He specifically mentioned emerging markets such as the Internet of Things, wearables, sensors and advanced driver assistance systems in automotive electronics. "These are very different and diverse markets, and the key is to achieve heterogeneous integration."

SiP has been used in high-bandwidth memory in wearable devices, some of which are usually the smallest form factors in consumer electronics. "The main reasons for using SiP are size and heterogeneous integration," Ray said.

Lessons Learned

However, it has taken quite a while for SiP to be considered a solution. In fact, it has been nearly a decade since OSATs, foundries and IDMs began to seriously develop these packaging methods.

“Like all the other OSATs, STATS ChipPAC has been focused on SiP technology development,” Ray said. “We’ve really worked hard on the design and assembly.” The company has also moved to system-level testing, combining RF and digital tests to ensure that the SiP is functioning properly.

A lot of work in the process was also completed through collaboration.

“The most important lesson we learned is that we have to work closely with the customers we work with,” Chang said. “Just because you can make a SiP doesn’t mean you can make a SiP solution. Working closely with customers and letting them tell you what they need in terms of hardware and software is the key to a successful SiP. Anyone can put together Lego bricks, but we realized we needed to work with our customers to really put the Lego bricks together into a solution that they could bring to market.”

Although the packaging house will usually provide support for the firmware, in most cases the customer will provide the necessary software.

However, the clear trend is that SiP technology will continue to develop in the market and will be more widely used in semiconductor manufacturing in the next few years. As fewer and fewer companies are able to follow Moore's Law into the single-digit nanometer range, SiP provides another direction for development. As more examples of this technology can be used with off-the-shelf components, its popularity is expected to expand significantly.

Today is the 1344th issue of content shared by "Semiconductor Industry Observer" for you, welcome to follow.

Follow the WeChat public account Semiconductor Industry Observation , reply to the keyword in the background to get more content

Reply Ambition , see "Apple's Ambition for a Chip Empire"

Reply Zhang Rujing , read "The Three Falls and Three Rise of Zhang Rujing, the Godfather of China's Semiconductor Industry"

Reply Domestic , see "The biggest beneficiary behind the rise of domestic mobile phones"

Reply to ASR and read "Behind ASR's Acquisition of Marvell MBU: A Love-Hate Story about RDA"

Reply to IC , read "Understanding the IC Industry Structure and Competitive Relationship in One Article"

Reply Exhibition , see "2017 Latest Semiconductor Exhibition and Conference Calendar"

Reply Submit your article and read "How to become a member of "Semiconductor Industry Observer""

Reply Search and you can easily find other articles that interest you!

Moore invites you to join the elite WeChat group

Click to read the original text and join the Moore Elite