Hardcore domestic EDA has entered the era of intelligent computing innovation

Generative AI has triggered the rapid expansion of the intelligent computing industry. Computing power has become the key driving force in the digital age and the cornerstone and embodiment of the country's scientific and technological strength. In the intelligent computing system, chips provide basic computing power support for the entire architecture. The number of parameters for each large model training and reasoning is growing exponentially, driving the explosive demand for autonomous computing chips such as GPU and CPU chips as computing power infrastructure. At the same time, the intelligent computing field has also brought multiple challenges to chip design. The complexity of chips has increased significantly. The strict time to market requires that the design and verification work be more accurate and efficient, and the requirements for system-level design and software and hardware collaboration are also more complex. These new challenges have subverted the traditional chip design methods of the past, while continuing to increase the complexity of EDA tool research and development.

Intelligent computing power based on GPU and AI chips is more efficient and can meet the needs of concurrent processing of large amounts of data. It uses 400G/800G high-bandwidth, low-latency networks to support large amounts of data transmission. At the same time, the massive computing power demand relies on AI servers, which are equipped with high-computing GPU chips. At the system level, PCB, as the base of the computing chip and the signal transmission channel, is crucial to improving server performance.

The outbreak of the era of intelligent computing has put forward a strict timetable for the support of domestic EDA, and time is running out. In order to meet the high demand driving force brought by the era of intelligent computing, the domestic supercomputing/intelligent computing chip industry faces multiple restrictions in design, tools and manufacturing, as well as complex system application software and hardware requirements, and very strict product launch time. The demand for EDA in the field of chip design in China is different from the past. How to break the deadlock has brought new challenges to the entire industry chain. As the core link of the chip industry, the domestic EDA industry is facing severe challenges, but also ushering in huge development opportunities and broad growth space.

All of the above factors drive China's high-end digital chip design to face three urgent demands: first, there is no doubt about the problem of domestic EDA tools; second, improving chip performance at the system level and solving the challenge of software and hardware collaboration, starting the consideration of system linkage design from an earlier stage; third, better supporting the needs of domestic large digital chip customers, including the latest high-speed interface IP and system-level design tools brought by the chiplet era.

As a leading domestic integrated circuit design EDA and industrial software company, Shanghai Hejian Industrial Software Group Co., Ltd. ("Hejian Gongruan") has been widely recognized by the domestic integrated circuit industry for its innovation speed and hard-core technical strength of launching more than 20 products in three years. While answering the questions given by the times, the company has also led the new trend of domestic EDA in industrial development, technological innovation and ecological improvement. Hejian Gongruan's innovation strategy has also been upgraded from solving key bottleneck problems to creating technological advantages, benchmarking the performance of international monopoly products, in order to cope with the technical challenges brought by the current intelligent computing chips, and provide high-level digital chip EDA and IP solutions.

On September 24, during the IDAS 2024 Design Automation Industry Summit, the "2024 Hejiangongsoft Annual New Product Launch Conference" was grandly held. At the conference, a number of domestically developed EDA and IP products were launched. Many of these product technologies have reached the internationally advanced performance level, providing a strong impetus for China's local EDA technology breakthroughs.

Hejian Gongsoft product launch event

At this press conference, Hejian Software released 11 innovative products, including UVHP, the first domestic hardware simulator that can be expanded to 46 billion logic gates, a new generation of single-system advanced prototype verification platform, DFT full-process platform, electronic system design tools and five high-speed interface IP products.

This annual product launch is a reflection of Hejian Software's solid development path of adhering to its original aspirations, recognizing the situation and taking multiple measures. In response to the multiple challenges brought by the rapid development of large-scale computing clusters to the design of digital large chips, Hejian Software has released a number of innovative products to provide solutions, including computing power main chip solutions, storage solutions, interconnection solutions and system solutions.

Diao Yanqiu, Vice Chairman of EDA² and CIO of Shenzhen HiSilicon Semiconductor Co., Ltd., representatives from academia such as Tsinghua University, Fudan University, and Shanghai University, as well as executives and customers of well-known semiconductor companies, totaling more than 400 representatives, attended the new product launch conference of Hejian Gongsoft.

At the press conference, Mr. Pan Jianyue, Chairman of Hejian Software, delivered an opening speech, and Mr. Diao Yanqiu, Vice Chairman of EDA², delivered a special speech. Mr. Pan Jianyue, Chairman of Hejian Software, said that Hejian Software has the vision of becoming a world-class EDA company, and aims to provide the Chinese integrated circuit industry with innovative EDA tools at the international leading level, which is in line with the country's important requirements for accelerating the development of new quality productivity. Throughout history, EDA development has always been at the forefront of the integrated circuit industry and led innovation. Since its inception, Hejian Software has always focused on product technology, maintained closed-door research and development, and laid a solid foundation. In a few years, Hejian Software has grown from a start-up to a leading domestic digital chip EDA company, and has also crossed over to multiple fields such as system level and IP. The EDA and IP products launched are aimed at iterating to global competitiveness. At present, Hejian Software has become the first domestic supplier that can provide "EDA+IP+system level" joint solutions for digital large chip design, refreshing the Chinese speed of EDA research and development and leading the era of domestic EDA innovation. Pan Jianyue emphasized that Hejian Software has received support from many users and partners along the way. In the future, Hejian Software will continue to maintain technological breakthroughs and product innovation to help the progress of domestic integrated circuit design companies and even the global industry.

Pan Jianyue, Chairman of Hejian Gongsoft, delivered a speech

The highlight of this conference was the release of EDA innovation trends and 11 new products by the technical expert team of Hejian Gongsoft, led by Hejian Gongsoft's CTO Mr. He Peixin. These products cover multiple fields including digital front-end, digital back-end, system level and interface IP. Facing the global competition for AI computing centers, my country is also vigorously planning data center computing clusters. The construction of intelligent computing centers has brought more complex and urgent challenges to chip design and systems. CTO Mr. He Peixin explained the development trend of EDA technology and Hejian Gongsoft's innovative strategic layout.

He Peixin, CTO of Hejiangongsoft, delivered a keynote speech

Specifically, the eleven innovative products released by Hejiangongsoft are as follows:

Since its establishment, Hejian Software has been aiming at the international advanced level, developing multiple product lines in parallel. While achieving innovation leadership in digital chip EDA technology, it has also achieved a number of innovative results in the field of digital chip design and verification, which is more technologically advanced and more challenging, filling the technical gaps in key points of some domestic EDA tools, demonstrating Hejian Software's strong R&D strength and customer support capabilities. In particular, it has achieved rapid coverage in the IP field, and has now become the first domestic company to simultaneously deploy EDA+IP, and has been successfully taped out by many commercial customers and commercially deployed by hundreds of customers.

Application areas such as AI intelligent computing, HPC supercomputing, AD/ADAS intelligent driving, 5G, and ultra-large-scale networks are driving the scale, functional integration, and software and hardware system-level complexity of chip design to increase significantly. This places higher demands on the capabilities of verification tools and brings challenges to verification in diverse scenarios. In addition to providing faster and more accurate compilation and more efficient debugging capabilities for chip design and development, verification tools must also have a more flexible and unified full-scenario verification platform. This not only improves fault correction efficiency and verification throughput, but also reduces the risk of large-scale complex chip tape-outs, and provides powerful digital twin capabilities for software and hardware collaborative simulation verification.

UniVista Hyperscale Emulator (UVHP) is the first domestically developed hardware emulator that can be expanded to 46 billion logic gates and supports further expansion of multiple systems, which can greatly improve the efficiency of simulation and verification and shorten the simulation and verification cycle of ultra-large-scale chips. The ultra-large-capacity hardware simulation acceleration platform UVHP is based on the new generation of proprietary hardware simulation architecture independently developed by UniVista, using advanced commercial FPGA chips, original high-performance RTL synthesis tool UVSyn, intelligent fully automatic compiler, and rich high-speed and low-speed interface and storage model solutions, providing strong support for the simulation and verification of ultra-large-scale ASIC/SOC.

UVHP, the hardware simulation acceleration verification platform newly launched by Hejian Software, has achieved a new height in energy efficiency and capacity for domestically developed hardware simulation acceleration platforms. The platform has increased the computing power of the hardware simulation system to the data center level, and the system scale supports adjustable gates from 160 million to 46 billion. It is the largest capacity among similar domestic products, and its performance is comparable to that of international advanced products. The full-scenario verification mode includes a variety of solutions such as pure hardware environment, XTOR and Hybrid, providing powerful computing power support for chip system-level hardware and software collaborative design and verification.

Zhang Yalin, COO of Enflame, said: "We are a long-term strategic partner of Hejian Software. In our previous computing chip projects, Hejian Software's UVHS dual-mode tool was used as the main verification platform. With its excellent performance and comprehensive intelligent computing solutions, it greatly improved the development efficiency of our AI software algorithms and won unanimous praise from the engineering team. We have always expected Hejian Software to launch a higher-integration, large-capacity hardware accelerator. Now the advent of the UVHP platform fills the gap in domestic commercial hardware accelerators at the scale of thousands of FPGAs. We look forward to the performance of UVHP and its supporting virtual platform and hybrid solutions in future projects, and will continue to work with Hejian Software to jointly promote the development of domestic computing platforms."

FPGA prototyping platforms can achieve faster software running speeds, significantly shorten software running time and verification iteration cycles, and also make it possible to design and develop digital twins of software and hardware in collaboration, helping to accelerate the launch of chips. As challenges such as the complexity and flexibility of user designs continue to emerge, chip verification urgently needs a larger-scale single-system prototyping platform that is both flexible, easy to use, and has higher performance.

PHINE DESIGN Advanced Solo Prototyping (PD-AS), a new generation of commercial-grade, single-system advanced prototyping verification platform, is launched by PHINE DESIGN Advanced Solo Prototyping (PD-AS), which is equipped with AMD's new generation of ultra-large adaptive SoC - AMD Versal™ Premium VP1902 Adaptive SoC. It adopts advanced technology and improves the overall equipment performance by more than two times. It is also equipped with a flexible and convenient operation interface and a rich variety of interface solutions, which can cover a larger scale of chip verification scenarios. It will be widely used in 5G-WIFI communications, intelligent computing, AIoT, smart cars, RF-navigation, RSIC-V IP, VR/AR and other industries.

Xu Tao, Chairman and CEO of Saifang Technology, said: "Efficiency is crucial in the development and verification process. Through advanced design environments, Saifang Technology is able to quickly customize CPUs that meet customer needs, and verification and software verification are key links in ensuring quality. Customers' expectations for high-quality products prompt us to conduct comprehensive verification of all RISC-V IPs, including functional verification, regression testing, and verification of the entire software stack. To this end, we use the PD-AS series 1902 platform, a single-system advanced prototype verification platform from Hejiangong Software, and the full-scenario verification hardware system UVHS to carry out these tasks. The former is used for single-core and dual-core development, while the latter is suitable for larger systems with more than four cores. Through these platforms, Saifang is able to execute trillions of cycles per day, greatly improving the verification efficiency and problem identification speed during the development process.

As product complexity and scale continue to increase, Hejiangongsoft's ultra-large capacity hardware simulation acceleration verification platform UVHP will continue to support Saifang's future project development. UVHP's excellent performance and RTL debugging capabilities will help Saifang achieve rapid verification and debugging in more complex designs and accelerate the development process of complex RISC-V cores."

Hejian Gongsoft's new generation PD-AS prototype verification platform can be used in chip verification fields such as SoC and IP, adapting to various verification scenario requirements, reducing the testing process, and accelerating chip launch. The platform has a larger capacity and an equivalent number of logic gates of approximately 100 million, more than twice that of the previous generation of products; faster speed and richer interface expansion solutions cover as many application scenarios as possible.

In order to meet the demand for high computing power in scenarios such as artificial intelligence, data centers, and autonomous driving, the size and scale of chips are getting larger and larger, with single-chip transistors reaching tens of billions or even hundreds of billions. At the same time, the application of high-level processes and advanced packaging technologies such as Chiplet has greatly increased the integration and complexity of chips. The probability of chip failure during the design and manufacturing process has increased significantly, and higher requirements have been placed on chip testing DFT solutions. It is necessary to quickly and accurately detect faults, repair or avoid faults to improve yield. At the same time, it is necessary to further improve test coverage and shift some test processes to the left to reduce defect escape rates and avoid increasing costs or delaying product time to market.

Hejian Software announced the launch of UniVista Tespert, a full-process platform for design for testability (DFT) with domestic independent intellectual property rights. The platform integrates a series of efficient tools, including the latest efficient defect diagnosis software tool UniVista Tespert DIAG, the efficient memory cell built-in self-test software tool UniVista Tespert MBIST, and the test vector automatic generation tool UniVista Tespert ATPG previously launched by Hejian Software. UniVista Tespert is committed to providing engineers with more efficient and higher-quality complete chip test platform tools to meet the challenges of modern chip design complexity and packaging technology, and help customers improve product quality and market competitiveness.

The latest UniVista Tespert DIAG is an innovative and efficient defect diagnosis software tool. It has independently developed an efficient and accurate diagnosis engine, adopts a new generation of data structure, and supports compressed and uncompressed test vector diagnosis technology. Its graphical interface provides a panoramic defect comparison, helping engineers quickly locate and solve systemic defects, greatly improving chip testing efficiency and accelerating product time to market.

UniVista Tespert MBIST, launched at the same time , is an advanced memory cell self-test tool that integrates advanced IJTAG interface protocols, provides an intuitive and easy-to-use graphical interface, supports multiple test algorithms and a flexible design rule checking engine. Through the UVTespert Shell automation platform, it effectively improves the efficiency and reliability of test settings, especially optimized for advanced processes such as FinFET, and provides customers with a comprehensive memory cell test solution.

Wang Haijin, senior director of Analog Semiconductor, said: "UniVista Tespert, the full-process DFT platform of Hejian Gongsoft, provides us with a comprehensive solution in the field of testing, which greatly improves the efficiency and reliability of our product testing. What is more worth mentioning is that UniVista Tespert DIAG's graphical interface and efficient diagnostic engine enable us to locate and solve chip defects more quickly, which is crucial to the progress of our project. As a supplier of analog and mixed analog and digital chips and solutions, Analog Semiconductor focuses on chip design in the fields of automotive intelligent drive, linear products, data converters, etc., and its products are mainly aimed at the industrial and automotive markets. The in-depth cooperation with Hejian Gongsoft will help Analog to provide customers with high-quality chips and provide underlying chip support for the world's technological and intelligent development."

Lu Yinpeng, DFT Technology Director of Qingxin Semiconductor Technology (Shanghai) Co., Ltd., said: "The UniVista Tespert platform from Hejian Software provides us with powerful DFT tools to help us cope with the challenges of complex chip design and testing, and improve product quality and market competitiveness. When we use UniVista Tespert MBIST, we find that the tool is very powerful for memory cell test management, which provides our chip design team with more design freedom. We believe that this tool can be widely used and bring more accurate and efficient solutions to the chip manufacturing industry."

UniVista Tespert is one of the important products in Hejiangongsoft's broader digital realization EDA product portfolio. It has been successfully deployed in domestic leading IC companies in the fields of automotive electronics, high-end process chips, etc., and has been applied to more than 50 different types of chip tests.

Hejian Software announced the launch of five new domestically produced high-speed interface IP solutions with independent intellectual property rights, providing users with innovative, highly reliable, high-performance network IP, storage IP and chiplet interface IP solutions to cope with the many challenges brought about by the era of intelligent computing, such as network interconnection, advanced packaging integration, and high data throughput.

With the rapid development of intelligent computing, data centers have gradually been upgraded to intelligent computing centers, and high-performance computing chips have also transitioned from CPU/DPU to high-computing chips such as AI/GPU. In order to give full play to the performance of high-computing chips, large-capacity, high-bandwidth, high-speed, and low-power memory solutions have become an important development direction. In high-computing scenarios, limitations on memory capacity or bandwidth will lead to high memory access latency and low efficiency, which seriously restricts the performance of computing chips. In addition, with the continuous increase in data transmission rates, chips not only need to ensure high data throughput, but also must take into account low power consumption, which has become one of the key focuses of architectural design.

In order to ensure the high performance and low power consumption of the chip and cope with the development of application scenarios such as AI, ML, and HPC, Hejian Software has launched a domestically produced Memory interface solution, including:

In the era of large AI models, distributed training performed by computing clusters consumes huge amounts of communication between nodes, making the communication network a key factor restricting the efficiency of large model training. In addition to training chips, inference chips require larger-scale networking than ever before to complete the calculation of larger tokens. Network scale, network performance, and reliability are becoming prominent issues restricting the efficiency of computing clusters. More and more chips are implementing ultra-large-scale networking solutions through RoCEv2 networks based on Ethernet switches. In order to ensure that large computing power chips can have perfect network performance, many AI chip companies have been faced with new challenges in designing and verifying network functions.

Hejian Software has newly launched UniVista RDMA IP, a domestically leading high-bandwidth, low-latency, and high-reliability intelligent computing network IP solution, to support the intelligent computing Wanka cluster. Its main functions include supporting a complete RoCEv2 transport layer, network layer, link layer, and physical coding layer that support 200G and 400G bandwidths. It can help chip designers achieve fast RDMA function integration and solve the high-bandwidth demand problem of intelligent computing chips. It can be widely used in the design of various types of chips such as AI, GPU, and DPU. Compared with traditional 25G/50G RDMA interconnection solutions, it has more advanced performance and has been successfully deployed and applied in domestic leading IC companies in fields such as AI and GPU.

• Higher bandwidth utilization: Supports overclocking point applications, providing 10% more bandwidth than standard Ethernet; supports flexible and configurable message headers, including configurable preamble, IPG, and MAC frame headers; supports ultra-long messages, with a maximum message length of 32K bytes.

• Higher reliability: Supports end-to-end retransmission of the RDMA transport layer, with a retransmission completion time of 10us; provides end-to-end retransmission based on the Ethernet MAC layer, with a retransmission completion time of us; supports point-to-point retransmission of the Ethernet PHY layer, with a retransmission completion time of 100ns.

• More flexible networking: Supports point-to-point direct connection based on Ethernet PHY layer protocol; supports Ethernet PHY configuration 1-to-2, 1-to-4, and flexibly supports full interconnection of 8 cards, 16 cards, and 32 cards; the number of RDMA QPs and WQEs is configurable, and can be switched with the direct connection protocol.

• Lower latency: Optimize the FEC low latency mode to further reduce the FEC decoding delay based on the existing RS272 algorithm; provide PAXI direct connection mode to achieve C2C connection through the Ethernet physical layer to reduce latency; simplify UDP/IP and MAC layer protocols and provide a simplified packet header mode.

Hejiangongsoft's high-speed interface IP solution has achieved a breakthrough in domestic technology, leading to performance breakthroughs and explosive development of high-computing chips in the fields of intelligent computing, HPC, communications, autonomous driving, and industrial Internet of Things.

With the continuous development of electronic system technology, the core functions of products rely heavily on high-performance large-scale integrated circuits. The widespread application of large-scale, high-performance integrated circuits has made the types, quantities, and system interconnections of electronic systems extremely complex. To achieve accurate descriptions of complex systems and to ensure the correctness and reliability of electronic system design, more stringent requirements have been placed on the updating of PCB and schematic design methods and processes. Large-scale, miniaturized, high-density, and high-speed have become important development trends for board-level systems. The UniVista Archer platform is the first domestically developed, high-performance, large-scale PCB and schematic design tool. The scale of PCB design it supports has reached the domestic advanced level, enabling higher-density layout and routing, and ensuring faster software operation speeds, helping to develop more intelligent electronic system products.

Hejian Software announced the launch of UniVista Archer, a new generation electronic system design platform. As the first domestically produced high-end large-scale PCB design platform with independent intellectual property rights, it meets the increasingly complex electronic system design needs, solves the design and simulation challenges brought by high-speed, multi-layer PCB design, and brings higher performance and reliability to electronic system and PCB board-level design engineers. It also supports the import of customer historical design data and is easy to learn and use. The UniVista Archer platform includes two products: UniVista Archer PCB, a leading integrated PCB design environment, and UniVista Archer Schematic, a board-level system circuit principle design input environment. It adopts a new advanced data architecture, and the performance of some products has been greatly improved. It has an accurate insight into the needs and habits of users, greatly improves the user experience, meets the complex functional needs of users, and provides an integrated intelligent design environment for modern complex electronic systems.

Wu Zhenhai, senior vice president of Huaqin Communication Technology Co., Ltd., said: "Hejian Gongsoft's UniVista Archer PCB and UniVista Archer Schematic products have been designed and verified in multiple of our product lines. During the design cycle using Hejian Gongsoft's tools, the design data is accurate and meets our company's design requirements. In addition, Hejian Gongsoft's PCB tools support the import of mainstream PCB design data in the industry, and the integrity and restoration of the imported data are also excellent. In addition to the product itself, the support and response speed of Hejian Gongsoft's technical team have made us fully appreciate the advantages of localized EDA tools."

Hejian Software now provides a full-process solution for electronic system-level EDA covering "component library + data management + process management + design tools". In the high-end market of system-level EDA tools, Hejian Software's products are fully competitive.

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