BCD Technology Popularization: A Unified Approach to Analog, Digital, and Power Design

Latest update time：2024-08-19

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Since its inception, BCD technology has taken advantage of the integration of two major technologies (polysilicon gate CMOS and DMOS power architecture) on the same chip. Its compatibility with bipolar components enables the creation of SoCs (systems on chip) that combine digital and analog control with efficient power management sections. The generation of BCD processes is based on CMOS baselines and geometric scaling rules for new lithography nodes to achieve an overall reduction in area and cost of all integrated functions. Historically, the development of BCD technology platforms has been driven by key application areas such as hard disk drives for computing and motion control for industrial applications.

BCD (Bipolar CMOS DMOS) is a process for driving high-voltage components, and is widely used in various applications such as audio amplifiers, RF (radio frequency), and the automotive industry. It is a key technology for power ICs. The process involves bipolar for precise analog functions, CMOS for digital design, and DMOS for power and high voltage. This means that a single chip has three functions as shown in Figure 1.1. The design of these three functional parts has different development and optimization standards.

However, their integration is essential to achieve correct system functionality. Each part cannot achieve the intended purpose of the system independently. They must work together to provide the desired overall functionality. In order to achieve optimal performance and minimize self-heating due to dissipation, it is important to place the different parts as close to each other as possible. This proximity reduces parasitic effects, minimizes signal delays, and enhances thermal management by allowing efficient heat dissipation throughout the chip, as shown in Figure 1.2.

BCD (Bipolar CMOS DMOS)

Typical BCD technology provides low voltage logic CMOS transistors, high voltage transistors, diodes, resistors and MIM capacitors in the same process. BCD process has parasitic bipolar transistors and is very suitable for making analog circuits such as bandgap references.

Figure 1.1

Figure 1.2

Advantages of using BCD technology:

Improve system reliability
Reduce electromagnetic interference
Smaller chip area
High energy efficiency

BCD Technical Architecture

Figure 2.1

C- Collector, B- Base, E- Emitter, S – Source, G – Gate, D – Drain, B – Body

Figure 2.1 above shows the typical BCD technology architecture.

Figure 3.1 above shows the BCD technology process flow.

BCD process overview:

Start with a block base:

Thick silicon wafer.
Large amounts of p-type impurities are doped.

Epitaxial deposition:

A thin layer of slightly p-doped silicon is grown on the substrate.
Using epitaxial (epi) deposition technology.

Uses of epitaxial layer:

Serves as a starting point for subsequent manufacturing steps.
It is essential for semiconductor device manufacturing.

Doping level considerations (balanced doping level):

Substrate resistance:

It should not be too low to avoid excessive resistance in the substrate that would impair device performance.

The crystal structure of silicon should not be too high as it ensures that the manufactured devices have good electrical performance and reliability.

The process starts with a bulk substrate, which is a thick silicon wafer that is heavily doped with p-type impurities.

When current is injected into the substrate, the smaller the substrate resistance, the lower the noise and the higher the electrical stability. This is because the parasitic bipolar transistor formed by the substrate and the isolation ring is less likely to be triggered by a larger current.

Maintaining low substrate resistance helps minimize parasitic effects and improves the overall performance and reliability of semiconductor devices.

Next, we implant a buried layer, a highly N-doped region created by very superficial implantation of antimony (Sb) ions.

Subsequently, a new P-type epitaxial layer is grown over the buried layer to accommodate the active area.

Deep trench isolation is then implemented to achieve lateral isolation between different parts of the chip, where performance and noise suppression are critical. The technology involves etching deep trenches in the substrate and filling them with a dielectric material such as silicon dioxide (SiO2).

Deep trench isolation effectively isolates the active areas of semiconductor devices, reducing crosstalk, leakage currents, and other harmful interactions that can degrade performance and increase noise. This isolation technology is particularly important in high-performance integrated circuits, where precise control of electrical isolation is critical to achieve optimal functionality.

Subsequently, active areas are defined for the integrated circuit. Depending on the technology node and specific design rules, the active area on the semiconductor wafer can be allocated to a single device or multiple devices. This allocation depends on various factors, such as the required circuit functionality, layout constraints, and the level of integration required for the design.

In semiconductor design, it is crucial to prevent current flow between different active areas. This is usually achieved through effective isolation techniques such as local oxidation of silicon (LOCOS) or using shallow trench isolation (STI).

Next, we implant the wells that require the largest thermal budget (HV wells). Specifically, these are the isolation wells (isolated regions within the substrate that prevent electrical interactions between different parts of the circuit), the wells of the LD-MOSFETs (n-wells or p-wells to optimize their performance and isolate them from other components on the chip), and the bodies of the high-voltage n-MOS and p-MOS (isolated to ensure proper biasing and prevent unexpected current flow that could cause device failure or damage).

In semiconductor manufacturing, after the implantation process is completed, the substrate undergoes a thermal annealing process in a furnace. This annealing step is critical to activate the dopants implanted into the substrate and to repair crystal damage caused by the implantation process.

The annealing process typically involves heating the wafer to a high temperature in a controlled environment, allowing the dopants to diffuse into the silicon lattice and form the desired electrical junctions. This thermal treatment also helps to relieve stress in the crystal structure, thereby improving the overall quality and reliability of the manufactured semiconductor devices.

We also implanted the wells that require the lowest thermal budget (LV wells). After implantation, the substrate was subjected to necessary thermal treatment via rapid thermal annealing (RTA).

In semiconductor manufacturing, the gate oxide of MOSFET transistors is grown using an in-situ steam generation (ISSG) process. This method involves generating steam (H2O) in situ, typically by reacting hydrogen (H2) with oxygen (O2) at the surface of a wafer. The steam is then used to grow a thin layer of silicon dioxide (SiO2) that serves as the gate oxide.

For high voltage devices, the gate oxide is first grown to its required maximum thickness. Subsequently, a masking step is performed, where a mask is applied to define the areas where the oxide is required. The exposed areas of the oxide are then etched away, leaving the gate oxide only in the required areas. The gate oxide continues to grow, focusing on achieving the desired final thickness. This growth can be partially extended into the high voltage areas as needed, ensuring uniformity and proper insulation across the substrate.

After doping the thick polysilicon layer, high doses of boron or arsenic are implanted into specific areas where n+ or p+ regions are needed to create. Silicide layers are formed in specific areas where metal contacts are made. The formation of the silicide layer effectively transforms the semiconductor-metal junction into a metal-metal junction. The last step is the back-end of line (BEOL) process, which refers to the final stage of manufacturing involving metal interconnect integration.

Typically, MIM capacitors are used in BCD technologies because they minimize parasitic capacitance to the substrate. MIM capacitors are best implemented between the upper metal layers of the technology BEOL. Another advantage of MIM capacitors is that they can be stacked above active components, which can reduce chip size compared to other solutions.

The PMOS/NMOS devices in CMOS most commonly have four terminals (gate source drain body), but in our design, we have seven PMOS terminal and six NMOS terminal devices as shown in Figure 4.1 and Figure 4.2 below respectively.

The other three terminals in our device are:

DPW (Deep P-Well) - The Deep P-Well shields the N-well containing the PMOS transistor from collecting signal charges from the epitaxial layer instead of the N-well as the charge collection electrode.

ISO NBL (Isolation N-type buried layer) – used to achieve isolation between circuits operating at different voltages or to prevent noise coupling through a common P substrate. It acts as a buried layer of N-type dopants within a P substrate. This layer effectively isolates different areas of the substrate from each other, preventing unintended electrical interactions and reducing noise propagation between circuits. ISO NBL helps minimize noise coupling through the substrate.

SUB ISO (Substrate Isolation) - The large number of switches in the digital blocks may affect the performance of the RF and analog blocks, and vice versa. We can isolate the various blocks of the circuit from each other so that the coupling between the RF and digital blocks through the substrate is minimized. Of course, there are interactions between the power and ground lines that must be addressed separately.

This isolation makes the HVNW (high voltage N-well) and NBL (N buried layer) at different potentials.

The DPW terminal is connected to the ground wire, the NBL terminal is connected to the power line, and the SUB terminal is connected to the ground wire.

The layer information of the ISO ring is shown in Figure 5.1.

All the PMOS and NMOS device clusters are placed in an isolation ring as shown in Figure 5.2 below.

To process high voltage signals with typical MOS (metal oxide semiconductor) devices, the device terminals are usually floated, which enables the flexibility to handle high voltage signals while maintaining operational integrity and preventing electrical stress. In CMOS (complementary metal oxide semiconductor) processes, substrate floating does degrade performance, primarily due to the lower resistivity of the substrate.

To address the challenges associated with substrate floating and improve the performance of CMOS designs, a triple-well structure is used. This structure effectively isolates the transistor body and the deep N-well from the substrate, allowing for separate biasing. The effectiveness of the isolation varies with frequency due to parasitic capacitance and other factors. At low frequencies, isolation is generally effective because the off-state resistance between the isolated regions (e.g., between the deep N-well and the substrate) is high. This high resistance minimizes leakage currents and prevents direct coupling of signals between different regions.

Reference Links

https://www.design-reuse.com/articles/56607/bcd-technology-a-unified-approach-to-analog-digital-and-power-design.html

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