DRAM challenges its limits, 3D DRAM is expected to take over

Despite the pandemic and trade war tensions, the DRAM market grew throughout 2020 (revenue growth of 7%) and 2021 (revenue growth of 41%). Production constraints and strong demand growth in most segments are key factors in the booming DRAM business. DRAM remains the largest memory segment by revenue: in 2021, it reached $94 billion and accounted for more than 56% of the entire standalone memory market.

Amid semiconductor shortages and various global challenges, DRAM is expected to continue to grow in 2022, at an annual rate of about 25%. That’s not all, as DRAM will continue to expand in the long term and is expected to grow to over $150 billion in 2027, with a 9% CAGR from 2021-2027. However, cyclicality will still exist.

DRAM is a highly concentrated market, with three major players, Samsung (South Korea), SK Hynix (South Korea), and Micron (USA), together accounting for more than 93% of the total market. Taiwanese companies (Nanya, Winbond, Powerchip) together account for nearly 5% of the market. CXMT, an emerging DRAM player from mainland China, has also been selling DRAM products year after year, targeting the Chinese domestic market for client PCs and consumer applications.

Yole SystemPlus recently revealed the landscape of competing technologies through an extensive analysis of cutting-edge LPDDR5 memory. They noted that the improved performance and efficiency that comes with improved power management and small transistor process technology can reduce battery consumption in smartphones. The report noted that LPDDR5 devices reach speeds of 6,400Mbps, almost 1.5 times that of the previous generation of low-power DRAM memory. LPDDR5 packages are typically paired with system-on-chip processors and installed on a system-on-chip (SoC) package to establish direct and fast communication with the smartphone processor. SK hynix's LPDDR5 8Gb die is produced using the 1y technology node, as is Micron's 12Gb die, while Micron's 16Gb die is manufactured using the 1Dz technology node.

Samsung uses the 1Dz technology node to manufacture its 16Gb die, which improves die density compared to competitors. Scaling DRAM cell size becomes more complex with each node advancement; therefore, Samsung differentiates its manufacturing process by adopting EUV lithography to shrink DRAM cells while reducing patterning steps.

The LPDDR5 1Dz cell design used by Samsung is highly competitive compared to the LPDDR5 memory from Micron and SK hynix because Samsung produces relatively smaller memory cells than its competitors. Smaller DRAM cells result in denser memory dies, which may lead to a reduction in memory die size without affecting die capacity. Chip shrinking is important for improving productivity and is required for high-volume manufacturing to meet the demand for low-power DRAM memory while reducing the memory package footprint on smartphone boards.

Samsung is estimated to produce over 2,000GB of 1Dz LPDDR5 per 300mm wafer. Samsung’s cutting-edge LPDDR5 process combines cell shrinking and EUV lithography to achieve denser memory and fewer manufacturing steps, thus maintaining cost competitiveness.

DRAM scalability was expected to end several years ago, but new technology solutions have enabled the development of the third generation at 10nm (1z) and possibly beyond. Overall, DRAM scaling is very challenging and is slowing down compared to the past—both in terms of bit density (Gb/mm 2 ) and cost per bit ($/Gb)—but it keeps moving forward! Despite the growing technical challenges, DRAM will continue to be the workhorse memory technology as new technology solutions such as EUV lithography, hybrid bonding, and 3D DRAM will enable continued density scaling and performance growth.

Today, there is consensus that planar scaling – even with lithographic EUV processes – will not be enough to deliver the required bit density improvements throughout the next decade. The industry urgently needs breakthroughs in materials and architecture to enable further DRAM scaling to reduce costs, minimize power consumption, and increase speed. As a result, monolithic 3D DRAM (the DRAM equivalent of 3D NAND) has been considered by major equipment suppliers and leading DRAM manufacturers as a potential solution for long-term scaling. Yole’s analysts believe that this novel 3D technology could enter the market in the 2029-2030 period.

Processor-memory interfaces are also evolving rapidly to meet the needs of emerging data-intensive applications: memory sizes must increase, as must the bandwidth between memory and the CPU. Various interfaces and protocols are under development, including HBM3, recently announced by JEDEC (January 2022), and CXL, which is gaining adoption as a “far memory” interconnect. Major players (e.g. Samsung-Xilinx, SK Hynix) have recently introduced new memory processing technologies to the market to overcome the so-called “memory wall”.

Overall, major companies in the DRAM memory ecosystem are exploring a variety of different solutions, and we believe that technological challenges will not prevent DRAM progress, although there is a risk of slowdown due to the need for further innovation and investment.

Currently in the memory market, NAND Flash, which can compete with DRAM, has entered 3D stacking as early as 2015 and has begun to transition to 100+ layer stacking. However, the DRAM market is still in the exploratory stage. In order to make 3D DRAM popular and mass-produced as soon as possible, major manufacturers and research institutes are also working hard to find breakthrough technologies.

HBM (High Bandwidth Memory) technology can be said to be the main representative product of DRAM's development from traditional 2D to 3D, opening the way for DRAM 3D. It mainly uses Through Silicon Via (TSV) technology to stack chips to increase throughput and overcome the bandwidth limitation in a single package. Several DRAM dies are stacked vertically and connected with TVS technology. From a technical point of view, HBM makes full use of space and reduces area, which is in line with the development trend of miniaturization and integration in the semiconductor industry, and breaks through the bottleneck of memory capacity and bandwidth, and is regarded as a new generation of DRAM solutions.

In addition to HBM, researchers have also begun to work on capacitor-free technology in an attempt to solve the current problem. In fact, regarding capacitor-free, there have long been technologies such as Dynamic Flash Memory, VLT technology, and Z-RAM. However, recently, IMEC, an independent research group in the United States and Belgium, demonstrated a new capacitor-free DRAM at the 2021 IEDM. This new type of DRAM is based on IGZO (indium-gallium-zinc-oxide) and is fully compatible with 300mm BEOL (back-end-of-line), with >103s retention and infinite (>1011) endurance.

According to reports, these results were obtained by researchers after selecting the best integration scheme for a single IGZO transistor, and this best integration scheme is a post-gate integration scheme with buried oxygen tunneling and self-aligned contacts. With this architecture, the gate length of IGZO TFTs (thin-film transistors) can be reduced to an unprecedented 14nm while still maintaining a retention of more than 100s. The retention rate at small gate lengths can be further optimized by scaling the threshold voltage (Vt) through EOT (equivalent oxide thickness), improving contact resistance, and reducing the thickness of the IGZO layer. When the thickness of the latter is reduced to 5nm, even the oxygen tunneling and annealing steps in O2 can be omitted, greatly simplifying the integration method.

(a) Schematic and (B) TEM image of a single IGZO transistor in a gate-last architecture with oxygen tunneling and 14nm gate length.

In fact, at the 2020 IEDM, imec demonstrated this capacitor-free DRAM for the first time, and it set off a heated discussion at the time. According to news in 2020, this DRAM included two IGZO-TFTs and no storage capacitors at the time, and this 2T0C (2 transistors 0 capacitors) DRAM architecture is expected to overcome the key obstacles to the density scaling of the classic 1T1C) (1 transistor 1 capacitor) DRAM, namely the large cut-off current size of Si transistors in small units, and the large area consumed by storage capacitors. However, in last year's "conceptual" demonstration, the IGZO TFT was not optimized for maximum retention, and there was a lack of evaluation of endurance (ie, the number of read/write cycles before failure). This year's capacitor-free DRAM has obviously been improved on the basis of last year, with both retention and endurance improved.

In general, the new DRAMs introduced this year have improved IGZO-based DRAM architecture and integration, enabling 2T0C DRAM memory with >10 3 retention, unlimited endurance, and gate length down to 14nm. More importantly, these breakthroughs make capacitor-free IGZO-DRAM a suitable candidate for realizing high-density 3D DRAM memory.

*Disclaimer: This article is originally written by the author. The content of the article is the author's personal opinion. Semiconductor Industry Observer reprints it only to convey a different point of view. It does not mean that Semiconductor Industry Observer agrees or supports this point of view. If you have any objections, please contact Semiconductor Industry Observer.

Today is the 3093rd content shared by "Semiconductor Industry Observer" for you, welcome to follow.