Why do we need Chiplet? Here’s what the AMD team said

Latest update time：2021-07-24

Reads：

Source: The content is compiled by Semiconductor Industry Observer (ID: icbank) from " next platform ", thank you.

Moore's Law is more than just a simple rule of thumb about the number of transistors; it's an economic, technological, and development force—and one that's powerful enough to drive some of the largest chipmakers to adopt future-proof architectural approaches.

This force has prompted some of AMD's key architects to re-route around the once-expected cadence of new technology development by adopting a chiplet approach.

We’ll get into more about why and what they consider later, but first, it’s useful to lay the groundwork.

AMD published its own internal estimates (right) with rough dates for the significant new process nodes that have emerged over the past decade or so. Note what happened with 14nm - the new technology had been evolving on a two-year cycle, but with this jump it moved to three years and continues to scale. This chart illustrates what we already know very well - Moore's Law is in decline, and soon, that decline will be sharp.

“The cost of manufacturing integrated chips has been climbing steadily, with the latest generations increasing dramatically due to added mask layers (e.g. for multi-patterning), more challenging and complex manufacturing (advanced metallurgy, new materials), etc.,” the AMD team explained. “Not only do processor manufacturers have to wait longer for each new process node, but they also have to pay more when the technology becomes available.”

The cost pressures are clear: aiming for higher density at this point will slow innovation, and as the AMD team points out, while the final price of a high-density device could offset some of the higher costs, “the industry is now facing photolithography mask limitations, which are a practical upper limit on how large silicon chips can be made.”

“Each chiplet is manufactured using the same standard lithography procedures as the monolithic case to produce a greater number of smaller chiplets. The individual chiplets are then tested for KGD. Now, for the same distribution of failures as the monolithic case, each potential defect results in only about a quarter of the silicon being discarded. The chiplets can be tested individually and then reassembled and packaged into the complete final SoC. The overall result is that each wafer can produce a significantly greater number of functional SoCs.”

The diagram above shows a hypothetical monolithic 32-core processor. AMD says their own internal analysis and product planning exercises indicate such a processor would require 777 square millimeters of die area in a 14nm process. "While still within the mask limits and therefore technically manufacturable, such a large die would be very expensive and put the product in a potentially uncompetitive position."

Most readers are already well aware of these trends, but they are worth highlighting because these pressures are at the heart of AMD’s broad chiplet strategy. This approach is costly, but that’s all. After all, if chiplets were a clear winner, the entire industry would have been chasing them.

“Chiplet design requires more engineering work to partition the SoC into the right number and types of chiplets. There are multiple possibilities, but not all meet cost constraints, performance requirements, ease of IP and chip reuse, etc,” the AMD team explained. It also requires significant R&D on the interconnect, involving longer routes, potentially with higher impedance, lower available bandwidth, higher power consumption, and/or higher latency. The complexity of the interconnect becomes even more overgrown with changes in voltage, timing, protocols, SerDes, and the ability to replicate all testing and debugging across more elements—all of which make chiplets less obvious.

Despite these complexities, most of the advantages of the chiplet approach became apparent in the first generation of AMD EPYC processors based on four replicated chiplets. Each of these had eight “Zen” CPU cores with two DDR4 memory channels and 32 PCIe lanes to meet performance targets. AMD had to leave some extra space for the Infinity Fabric interconnect between the four chiplets. The design team discussed the cost lessons learned from the first run:

"In 14nm process, each chiplet has a die area of 213mm2, and the total die area is 4*213mm2 = 852mm2. This means about 10% die area overhead compared to a hypothetical monolithic 32-core chip. Based on AMD internal yield modeling using historical defect density data on mature process technologies, we estimate that the final cost of the quad-chiplet design is only about 0.59 of the monolithic approach, despite a ~10% increase in total silicon consumption."

In addition to reducing costs, they were able to reuse the same approaches across products, including using them to build a 16-core part, double the DDR4 channels, and provide 128 PCIe lanes.

But none of this is free. Latency is introduced when chiplets communicate over the Infinity Fabric, and some memory requests must be handled with care because of mismatched numbers of DDR4 memory channels on the same chiplet.

These lessons were used in the second generation of 7nm Epyc processors. There was an incredibly rich discussion about the various trade-offs and technical challenges, as well as cost and performance. Included were the factors behind packaging decisions, co-design challenges, optimizations and similar approaches scaling across products.

“Beyond the technical challenges, implementing such a broad chiplet approach across so many market segments requires a lot of collaboration and trust between the technical teams, business units, and our external partners,” the team concluded.

“Product roadmaps across markets must be carefully coordinated and timed with each other to ensure the right silicon is available at the right time to launch each product. Unexpected challenges and obstacles can arise, and the world-class and passionate AMD engineering team is located around the world. The success of AMD’s chiplet approach is both a feat of engineering and a testament to the power of teams with diverse skills and expertise working together toward a common goal and shared vision.”

★ Click [Read original text] at the end of the article to view the original link of this article!

*Disclaimer: This article is originally written by the author. The content of the article is the author's personal opinion. Semiconductor Industry Observer reprints it only to convey a different point of view. It does not mean that Semiconductor Industry Observer agrees or supports this point of view. If you have any objections, please contact Semiconductor Industry Observer.

Today is the 2745th content shared by "Semiconductor Industry Observer" for you, welcome to follow.

Latest articles about

■TSMC's 2nm is too powerful, UMC is too miserable

■The United States has heavily funded this semiconductor technology

■Tesla is also snapping up HBM 4

■Intel's next-generation AI chip is exposed for the first time

■Nvidia releases its largest chip yet

■The Danish robot giant invites you to "do something" together

■Self-developed DPU released: Microsoft chip, full of firepower

■In the post-Moore era, optical computing chips have become the key to breakthrough, and domestic manufacturers have great potential!

■Open source software in crisis

■The global semiconductor equipment giants are all in trouble