Useful information | Senior engineers analyze PCB design skills of op amp circuits

Printed circuit board (PCB) routing plays a critical role in high-speed circuits, but it is often one of the last steps in the circuit design process. There are many aspects to high-speed PCB routing, and a large amount of literature has been written on this topic. This article mainly discusses the routing issues of high-speed circuits from a practical perspective. The main purpose is to help new users pay attention to the many different issues that need to be considered when designing PCB routing for high-speed circuits. Another purpose is to provide a review material for customers who have not been exposed to PCB routing for some time. Due to limited space, this article cannot discuss all issues in detail, but we will discuss the key parts that have the greatest effect on improving circuit performance, shortening design time, and saving modification time. Although this article focuses on circuits related to high-speed operational amplifiers, the issues and methods discussed here are generally applicable to the routing of most other high-speed analog circuits. When operational amplifiers operate in the very high radio frequency (RF) band, the performance of the circuit depends largely on the PCB routing. A high-performance circuit design that looks good on the "drawing" can only achieve mediocre performance if it is affected by careless and sloppy routing. Forewarning and attention to important details throughout the routing process will help ensure the expected circuit performance.

What information should be included in a schematic besides the usual reference identifiers, power consumption, and error tolerances? Here are some tips to turn an ordinary schematic into a first-rate one. Add waveforms, mechanical information about the enclosure, trace lengths, and blank areas; indicate which components need to be placed on the PCB; include trim information, component ranges, heat dissipation information, controlled impedance traces, comments, a concise description of the circuit's behavior... (and more).

Instructions to the layout engineer include: a brief description of the circuit's function, a PCB outline showing the location of inputs and outputs, PCB stack-up information (e.g., how thick the board is, how many layers there are, details of each signal layer and ground plane - power consumption, ground, analog signals, digital signals and RF signals); which signals are needed on each layer; where important components are required; the exact location of bypass components; which traces are important; which lines need controlled impedance traces; which lines need to match lengths; the size of the components; which traces need to be kept away (or close) from each other; which lines need to be kept away (or close) from each other; which components need to be kept away (or close) from each other; which components should be placed on the top of the PCB and which on the bottom. Never complain about having too much information to give others - too little? Yes; too much? No. A learning experience: About 10 years ago, I designed a multi-layer surface mount circuit board - there were components on both sides of the board. The board was fixed in a gold-plated aluminum housing with many screws (because there were strict shock protection specifications). The pin that provided bias feedthrough passed through the board. The pin was connected to the PCB by a solder wire. It was a complicated unit. Some of the components on the board were for the SAT setup. But I had clearly specified where they were. Can you guess where they were? On the underside of the board. It was not pleasant for the product engineers and technicians to have to take the whole unit apart, complete the setup, and then put it back together. I have never made that mistake since.

Just like in the PCB, location is everything. It is very important where you place a circuit on the PCB, where you mount its specific circuit components, and what other circuits are adjacent to it. Usually, the location of inputs, outputs, and power supplies is predetermined, but the circuits between them need to be "creative." This is why paying attention to wiring details will pay huge dividends. Start with the location of key components, considering the specific circuit and the entire PCB. Specifying the location of key components and the path of signals from the beginning helps ensure that the design will work as expected. Getting the design right the first time can reduce costs and stress-which shortens the development cycle.

Bypassing the power supplies at the amplifier's supply terminals to reduce noise is an important aspect of the PCB design process - whether for high-speed op amps or other high-speed circuits. There are two common configurations for bypassing high-speed op amps. Supply-to-ground: This method is the most effective in most cases, and uses multiple parallel capacitors to connect the op amp's power supply pins directly to ground. Generally speaking, two parallel capacitors are sufficient - but adding parallel capacitors may benefit some circuits. Parallel capacitors of different capacitance values ​​help ensure that the power supply pins only see a low alternating current (AC) impedance over a wide frequency band. This is especially important at frequencies where the op amp's power supply rejection ratio (PSR) rolls off. The capacitors help compensate for the amplifier's reduced PSR. Maintaining a low-impedance path to ground over many decades will help ensure that unwanted noise cannot enter the op amp. Figure 1 shows the advantages of using multiple parallel capacitors. At low frequencies, large capacitors provide a low-impedance path to ground. But once the frequency reaches their own resonant frequency, the capacitors become less capacitive and begin to become inductive. This is why it is important to use multiple capacitors: as the frequency response of one capacitor begins to roll off, the frequency response of another capacitor begins to come into play, so the AC impedance can be kept very low over many decades.

Figure 1. Capacitor impedance vs. frequency.

Start directly from the op amp's power pins; capacitors with the smallest capacitance and smallest physical size should be placed on the same side of the PCB as the op amp—as close to the amplifier as possible. The ground end of the capacitor should be connected directly to the ground plane with the shortest pins or traces. The above ground connection should be as close to the amplifier's load as possible to reduce interference between the power supply and ground. Figure 2 shows this connection method.

Figure 2. Shunt capacitors bypassing power supply terminals and ground.

This process should be repeated for the next largest value capacitor. It is best to start with the smallest value, 0.01 µF, and place a 2.2 µF (or larger) electrolytic capacitor with low equivalent series resistance (ESR) close by. A 0.01 µF capacitor in a 0508 case size has very low series inductance and good high frequency performance. Supply-to-supply: Another configuration uses one or more bypass capacitors across the positive and negative supply terminals of the op amp. This method is often used when it is difficult to configure four capacitors in the circuit. The disadvantage is that the case size of the capacitor may increase because the voltage across the capacitor is twice the voltage value in the single-supply bypass method. Increasing the voltage requires increasing the device's rated breakdown voltage, which means increasing the case size. However, this method can improve PSR and distortion performance. Because every circuit and layout is different, the configuration, number, and capacitance value of the capacitors should be determined according to the actual circuit requirements.

Figure 3. Typical operational amplifier circuit, (a) original design, (b) after considering parasitic effects.

In high-speed circuits, very small values ​​can affect circuit performance. Sometimes a few tens of picofarads (pF) of capacitance is sufficient. A related example: if there is only 1 pF of additional parasitic capacitance at the inverting input, it can cause a spike of almost 2 dB in the frequency domain (see Figure 4). If the parasitic capacitance is large enough, it can cause circuit instability and oscillation.

Figure 4. Additional spikes caused by parasitic capacitance.

When looking for problematic parasitic sources, there are a few basic formulas for calculating the size of the parasitic capacitances mentioned above that may be useful. Formula (1) is the formula for a parallel plate capacitor (see Figure 5).

(1) C represents the capacitance value, A represents the plate area in cm2, k represents the relative dielectric constant of the PCB material, and d represents the distance between the plates in cm.

Figure 5. Capacitance between two plates.

Strip inductance is another parasitic effect that needs to be considered. It is caused by long traces or lack of a ground plane. Equation (2) shows the formula for calculating trace inductance. See Figure 6. (2) W represents the trace width, L represents the trace length, and H represents the trace thickness. All dimensions are in mm.

Figure 6. Trace inductance.

The oscillation in Figure 7 shows the effect of a 2.54 cm trace at the non-inverting input of a high-speed op amp. Its equivalent parasitic inductance is 29 nH (10-9H), which is enough to cause a sustained low-voltage oscillation that lasts for the entire transient response period. Figure 7 also shows how a ground plane can be used to reduce the effect of parasitic inductance.

Figure 7. Pulse response with and without a ground plane.

Vias are another source of parasitics; they can cause parasitic inductance and parasitic capacitance. Equation (3) is the formula for calculating parasitic inductance (see Figure 8).

(3) T represents the thickness of the PCB and d represents the diameter of the through hole in cm.

Figure 8. Via hole dimensions.

Equation (4) shows how to calculate the parasitic capacitance caused by the via (see Figure 8).

(4) εr is the relative permeability of the PCB material. T is the thickness of the PCB. D1 is the diameter of the pad surrounding the via. D2 is the diameter of the isolation hole in the ground plane. All dimensions are in cm. A single via can add 1.2 nH of parasitic inductance and 0.5 pF of parasitic capacitance to a 0.157 cm thick PCB; this is why it is important to be vigilant when routing PCBs to minimize the impact of parasitic effects.

There is actually much more to discuss than what is covered in this article, but we will highlight some key features and encourage readers to explore the topic further. The ground plane acts as a common reference voltage, provides shielding, can dissipate heat, and reduces parasitic inductance (but it also increases parasitic capacitance). Although there are many benefits to using a ground plane, it must be implemented with care because it has some restrictions on what can and cannot be done. Ideally, one layer of the PCB should be dedicated to the ground plane. This will produce the best results when the entire plane is not broken. Never use the ground plane area on this dedicated layer to connect other signals. Because the ground plane can eliminate the magnetic field between the conductor and the ground plane, it can reduce the inductance of the trace. If an area of ​​the ground plane is broken, it will introduce unexpected parasitic inductance to the traces above or below the ground plane. Because the ground plane usually has a large surface area and cross-sectional area, keep the resistance of the ground plane to a minimum. At low frequencies, current will take the path of least resistance, but at high frequencies, current will take the path of least impedance. However, there are exceptions, and sometimes a small ground plane is better. High-speed op amps work better if the ground plane is moved away from under the input or output pads. Because the parasitic capacitance introduced by the ground plane at the input increases the op amp's input capacitance, it reduces phase margin and can cause instability. As seen in the discussion of parasitic effects, 1 pF of capacitance at the op amp input can cause significant spikes. Capacitive loading at the output—including parasitic capacitive loading—creates a pole in the feedback loop. This reduces phase margin and causes the circuit to become unstable. If possible, analog and digital circuits—including their respective ground and ground planes—should be separated. Fast rising edges cause current spikes to flow into the ground plane. These fast current spikes cause noise that can corrupt analog performance. The analog and digital grounds (and the power supplies) should be connected to a common ground point to reduce circulating digital and analog ground currents and noise. At high frequencies, a phenomenon called "skin effect" must be considered. Skin effect causes current to flow to the outer surface of a conductor—resulting in a narrower cross-section of the conductor, thereby increasing the DC resistance. Although the skin effect is beyond the scope of this article, here is a good approximation for the skin depth in copper wire (in cm):

(5) Low-sensitivity electroplated metal helps reduce the skin effect.

There are a variety of analog and digital signals on PCBs, ranging from high to low voltages or currents, from DC to GHz frequency ranges. It is very difficult to ensure that these signals do not interfere with each other. Looking back at the advice in the previous "Don't Trust Anyone" section, the key is to think ahead and develop a plan for how to deal with the signals on the PCB. It is important to pay attention to which signals are sensitive and determine what measures must be taken to ensure the integrity of the signals. The ground plane provides a common reference point for electrical signals and can also be used for shielding. If signal isolation is required, the first thing to do is to leave physical distance between signal traces. Here are some practical experiences worth learning from: Reducing the length of long parallel lines and the proximity of signal traces in the same PCB can reduce inductive coupling. Reducing the length of long traces on adjacent layers can prevent capacitive coupling. Signal traces that require high isolation should be routed on different layers and - if they cannot be completely isolated - should be routed orthogonal traces with the ground plane placed between them. Orthogonal routing can minimize capacitive coupling, and the ground line will form an electrical shield. This method can be used when forming controlled impedance traces. High-frequency (RF) signals typically flow on controlled-impedance traces. That is, the trace maintains a characteristic impedance, such as 50Ω (a typical value in RF applications). The two most common controlled-impedance traces, microstrip4 and stripline5, achieve similar results, but in different ways. Microstrip controlled-impedance traces, shown in Figure 13, can be used on either side of the PCB; it uses the ground plane directly below it as its reference plane.

Figure 13. Microstrip transmission line.

Formula (6) can be used to calculate the characteristic impedance of a FR4 board.

(6) H is the distance from the ground plane to the signal trace, W is the trace width, and T is the trace thickness; all dimensions are in mils (10-3 inches). εr is the dielectric constant of the PCB material. Strip controlled impedance traces (see Figure 14) use two ground planes with the signal traces sandwiched between them. This approach uses more traces, requires more PCB layers, is sensitive to dielectric thickness variations, and is more expensive—so it is usually used only in demanding applications.

Figure 14. Stripline controlled impedance trace.

The characteristic impedance calculation formula for stripline is shown in formula (7).

(7) Guard rings, or “isolation rings”, are another common shielding method for operational amplifiers. They are used to prevent parasitic currents from entering sensitive nodes. The basic principle is simple: a guard wire is used to completely surround the sensitive node, and the wire maintains or forces it to maintain (low impedance) the same potential as the sensitive node, thereby keeping the absorbed parasitic current away from the sensitive node.

Figure 15(a) shows the schematics of guard rings used in inverting and noninverting op amp configurations. Figure 15(b) shows typical layout methods for both guard rings in a SOT-23-5 package.

Figure 15. Guard ring. (a) Inverting and noninverting operation. (b) SOT-23-5 package. There are many other shielding and layout methods. For more information on this and other topics mentioned above, the reader is referred to the following references.

High-level PCB layout is very important for successful operational amplifier circuit design, especially for high-speed circuits. A good schematic is the basis of good layout; close cooperation between circuit design engineers and layout design engineers is fundamental, especially regarding the location of components and wiring. Issues that need to be considered include bypassing power supplies, reducing parasitic effects, using ground planes, the impact of operational amplifier packaging, and routing and shielding methods. 1. When designing PCBs, capacitors such as bypass filters at the chip power supply should be as close to the device as possible, with a typical distance of less than 3MM. 2. Small ceramic bypass capacitors at the power supply of the operational amplifier chip can provide energy for the high-frequency characteristics of the amplifier when the amplifier is in the input high-frequency signal. The choice of capacitor value is based on the frequency of the input signal and the speed of the amplifier. For example, a 400MHz amplifier may use 0.01uF and 1nF capacitors installed in parallel. 3. When we buy components such as capacitors, we also need to pay attention to their self-resonant oscillation frequency. Capacitors with self-resonant frequencies above and below this frequency (400MHz) are of no benefit. 4. When drawing the PCB, do not run other lines under the input and output signal pins of the amplifier and the feedback resistor, so as to reduce the mutual influence of parasitic capacitance between different lines and make the amplifier more stable. 5. The high-frequency performance of surface-mount devices is better and the size is small. 6. When routing the circuit board, the routing should be as short as possible. At the same time, pay attention to its length and width to minimize the parasitic effect. 7. For the treatment of power lines, the parasitic characteristics of the power lines are the worst DC resistance and self-inductance, so we try to widen the power lines as much as possible when laying them. 8. The current on the input and output connecting lines of the amplifier is very small, so they are easily affected by parasitic effects, which are very harmful to them. 9. For signal paths exceeding 1CM, it is best to use transmission lines with controlled impedance and terminations (matching resistors) at both ends . 10. Amplifiers drive resistive and capacitive loads. In order to solve the stability problem, a common technique is to introduce a resistor ROUT, and it is best to be close to the op amp. In this way, the capacitive load is isolated by using the series output resistor.

Source: Internet compilation. If copyright is involved, please contact us to delete.

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