Samsung will become the world's first foundry to provide 3D SiP next year, and 3nm will be put into trial production in 2020

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Samsung recently held the Samsung Foundry Forum 2018 (SFF) in Japan, where it released several important information. In addition to reiterating plans to start high-volume production (HVM) using extreme ultraviolet lithography (EUVL) in the next few quarters, and reiterating plans to use gate-on-a-gate FETs (GAAFETs) with 3-nanometer nodes, Samsung also added the new 8LPU process technology to its roadmap. In addition, the provision of 3D SiP in 2019 and the start of risk production of 3nm nodes in 2020 are also highlights.

Samsung Foundry’s overall roadmap was announced earlier this year, so at the SFF in Japan, Samsung reiterated some of its plans, also made some revisions, and provided some additional details about its future plans.

First, Samsung added a new process called 8LPU (low power ultimate) based on the 10nm process. According to Samsung's classification, this is a process prepared for SoCs that require high clock frequency and high transistor density. 8LPU is a further upgrade of the 8LPP technology platform, which may increase transistor density and boost frequency. Samsung's 8LPP technology was put into production last year. Based on the development of Samsung's 10nm node, the narrower minimum metal spacing can reduce the area by 10% (same complexity) and reduce power consumption by 10% (same frequency and complexity) compared to 10LPP. However, Samsung did not disclose how it improved 8LPU based on 8LPP, such as design rules, new libraries, and minimum metal spacing.

Samsung's 8LPP and 8LPU technologies are targeted at customers who need higher performance or lower power or higher transistor density than what the 10LPC and 10LPU processes can provide, but do not have access to Samsung's 7LPP or more advanced manufacturing technology EUVL. Risk production of 8LPU will begin in 2018, with high-volume production expected to begin next year at Fab S1 in Giheung, South Korea.

Last year, Samsung promised to start producing chips using 7LPP in 2018. It seems that Samsung has already started manufacturing 7LPP SoCs, but it may be limited to its parent company, because its MPW (Multi-Project Wafer) service schedule does not mention 7LPP. The 7LPP production technology will be the flagship process of Samsung Foundry, so it is likely to be used first for Samsung's mobile SoCs. At the same time, the process is also suitable for chips targeting HPC, ML, and AI. For example, Samsung is preparing dedicated IP for custom chips, including 100 Gbps + SerDes, etc.

At the forum, Samsung said it has installed multiple ASML Twinscan NXE:3400B EUVL step and scan systems at Fab S3 in Hwaseong, South Korea. Of course, it did not disclose the specific number, but it made it clear that the scanner's daily wafer (WPD) performance is in line with its mass production goals. In fact, since EUV will be used for HVM for the first time, Samsung foundry is not inclined to expand it beyond the design of specific customers (Samsung and Qualcomm have already selected 7LPP for Snapdragon 5G SoC, which will be produced in 2019).

Samsung will expand EUV lithography technology after building another production line at the Sanhua plant, which is expected to cost 6 trillion won (about 4.615 billion US dollars) and is expected to be completed in 2019, with HVM started in 2020. Therefore, Samsung's production using EUVL equipment will be limited to one plant for at least a few quarters, which may also be the reason why Samsung foundry developed 8LPP and 8LPU processes.

When the new line in Hwaseong is put into operation, Samsung promises to start risk trial production of 5/4 nm nodes. Samsung is preparing 5LPE, 4LPE and 4LPP technologies, and of course more may be added. Based on what Samsung has disclosed so far, they will have certain similarities, which will simplify the migration from 5LPE to 4LPP.

A slide presented by Samsung at SFF 2018 Japan indicated that Samsung expects chips using the 5/4 nm node to start risk production in 2019, suggesting that these process technologies will coexist rather than follow each other. Since Samsung has little reason to design competing manufacturing processes, it is more likely that its 5LPE will be used first for HVM in 2020, and then 4LPE/4LPP will use the EUV equipment added later, unless Samsung's roadmap changes significantly.

One thing to keep in mind is that Samsung’s 5/4 nm will be the last node the company will use with FinFET transistors, which is why it will be a “long” node used for many years to come, just like the 28nm technology used today.

One of the surprises Samsung announced was the start of risk production with its 3nm node in 2020, at least a year earlier than previously expected. Samsung’s 3nm will be the first node to use the company’s own GAAFET implementation, called MBCFET (multi-bridge-channel FETs), and will include at least two process technologies: 3GAAE and 3GAAP (3nm gate-all-around early/plus).

However, Samsung has not yet announced any targets for 3GAAE and 3GAAP, and it is difficult to say when the company will produce commercial SoCs based on MBCFET technology. What we understand today is that both technologies rely on EUVL, so before using it, Samsung must ensure that EUV provides the necessary yield and performance. Considering that Samsung is satisfied with the performance of the ASML Twinscan NXE:3400B EUVL step-and-scan system and expects WPD productivity to increase further, it is possible that it will be introduced to the 3nm node.

Although GAAFET is only a few years away, the technology of planar transistors will not go everywhere and will continue to evolve. Samsung Foundry will continue to support FD-SOI technology and will be a strong competitor to GlobalFoundries' 22FDX and 12FDX products.

Samsung Foundry intends to start risk production with its 18FDS in 2019, so HVM won’t be until 2020. The technology uses the same BEOL interconnects as Samsung’s 14LPE/14LPP (i.e., the BEOL originally developed for its 20nm planar process), but with new transistors and FEOL. Samsung promises that 18FDS will deliver 20% higher performance (at the same complexity and power), 40% lower power (at the same frequency and complexity), and 30% smaller die area compared to its 28FDS.

Of particular importance, 18FDS will support RF and eMRAM, enabling Samsung Foundry to meet the various application requirements of RF and embedded memory in the 5G era in 2020 and beyond.

Chip packaging technology has become increasingly important recently, as it has become increasingly difficult and expensive to integrate all the devices into a single processor. Samsung (like TSMC and GlobalFoundries) already offers many packaging solutions for complex products, such as FOPLP-PoP for mobile SoCs and I-Cube (2.5D) for HBM2 DRAM chips. Next year Samsung will offer its 3D SiP (system-in-package) solution, which will enable it to package various devices in a three-dimensional package with a very small area.

Samsung Foundry’s 3D SiP will be one of the industry’s first technologies for heterogeneous 3D SiP (currently all SiPs are 2D). The packaging solution will enable semiconductor contract manufacturers to assemble SiPs using components manufactured using completely different process technologies.

Source: Leifeng.com

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