Practical analysis | AC/DC buck converter circuit explanation

Latest update time：2021-09-04 03:38

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Offline devices such as smart meters or power monitors have electronic components that require non-isolated DC power below 10 W. Until now, the only practical way to provide low-power DC power from an AC source has been to use a very inefficient, unregulated resistor/capacitor divider after the rectifier, or a difficult-to-design flyback DC/DC converter.

Some advances in MOSFET technology and an innovative hysteretic buck controller gate have resulted in an ultra-low-cost DC power supply.

The complete converter is shown in Figure 1. The rectifier circuit uses a standard, fast switching rectifier diode bridge (D1) and an LC filter (L1 and C2), and the remaining components will be described in more detail.

Figure 1 AC/DC buck converter circuit

Basic Buck Converter

The TPS64203 is a hysteretic step-down converter designed to drive high-side pFETs with minimum on and off switching time requirements. Unlike traditional hysteretic converters, which have a switching frequency that varies with load current, the minimum on and off times fundamentally control the switching frequency when the converter operates in continuous conduction mode at high output power consumption levels. Other converters in the TPS6420x family actively avoid switching in the audible frequency range, effectively achieving maximum on and off times. The TPS6420x family was originally designed for battery-powered applications and has an input voltage range of 1.8V to 6.5V and very low quiescent current (maximum 35 μA). During startup, the TPS64203 is biased by Zener diode D2 and high-voltage resistors R2 and R3. After the 5V voltage rises, Schottky diode D4 allows the 5V output to drive the controller.

The power FET Q4 must have a high enough VDS voltage rating so that it is not damaged by the input voltage, and a high enough current rating to handle IPMOS(RMS) = IOUT(max) × √Dmax. Its package must also be able to dissipate PCond = (IOUT(max) × √Dmax)2 × RDS(on). Generally, high voltage P-channel FETs have an excessive gate capacitance or turn-on/off time, too high drain-source resistance (RDS(on)), too large threshold voltage (VTH), and/or too high a cost (i.e., sufficiently cost-effective) to manufacture the actual circuit shown in Figure 1. Since the high voltage line of 230VRMS + 10% tolerance is derived from the 350VPK AC line, the FET, filter, and input capacitors need to be rated for 400V.

The FQD2P40 is a relatively new, 400V P-channel MOSFET. With a 5.0Ω RDS(on) at a 10V gate drive and a total gate charge of less than 13nC, this FET can be easily switched by the controller with relatively less conduction and switching losses than older FETs, thanks to an innovative drive circuit consisting of Q2, Q3, C4, and D3. We chose the converter’s rectifying Schottky diode D5 because it has a voltage rating that blocks the input voltage, a peak current rating slightly higher than the output voltage, and an average current rating of IDiode(Avg) = (1 – D) × IOUT(max). With Dmax 5 V/120 V = 0.04 and such a low output power, the peak current rating and power dissipation are not an issue in either switch.

The LC filter of the buck power stage is designed as described in the TPS6420x family datasheet. With an input voltage higher than the output voltage, all TPS6420x controllers will operate in minimum on-time mode. Equation (1) calculates the recommended buck converter inductor at high line voltage, assuming an inductor ripple current coefficient of K = 0.4.

The relatively high value of K minimizes the inductor value and has proven to be acceptable because the steady-state output ripple requirement for this particular application is less than 0.02 × VOUT, or 100mVPP at high loads. After hysteresis, the TPS6420x controllers generally work best when there is some ripple in the output voltage, and an output capacitor with at least 50mΩ ESR is recommended to produce a ripple voltage of ΔVPP(ESR) = ΔIL × RESR, which generally far exceeds the capacitive component of the voltage ripple. Figure 2 shows the measured ripple for this application.

Figure 2 Output ripple at VIN=250 VDC and IOUT=500mA

Since the TPS64203 is hysteretic, its output voltage will have higher ripple at lower output power when it operates in pulse frequency mode. The measured operating frequency of the converter is about 32 kHz, which is consistent with the following expected values:

working principle

Bipolar transistor Q1 and resistors R4 and R5 form a constant-current driven level shifter that allows the low-voltage TPS64203 controller to operate the discrete gate drive circuit formed by Q2 and Q3. Like the controller, the level shifter is driven by Zener diode D2 at startup, and after startup the regulated 5V is driven through Schottky diode D4. The gate of power FET Q4 must be just overdriven to provide an acceptable RDS(on) for the required output current. Too much drive increases switching losses, while too little drive increases conduction losses. After some trial and error, we chose VGS ≈ 12 V.

Capacitor C4 and diode D3 are critical to the function of the driver circuit. The 12V gate drive level is set below the rectifier output voltage by selecting resistor R5. Diode D3 limits capacitor C4 to this level. Specifically, when the switch pin of U1 outputs a low signal to turn on the power FET, the signal is level-shifted to the base of Q3. Transistor Q3 turns on and quickly charges Q4's gate-source capacitance CGS to 12V. Without C4 and D3, turning off Q4 would render Q3 an expensive high-voltage bipolar transistor with its drain connected to ground. When the switch pin of U1 outputs a high signal to turn off the power FET, the signal is level-shifted to the base of Q2. Q2 turns on, effectively connecting Q4's gate to the input voltage. It is important to note that without capacitor C4 acting as a local power source, transistors Q2 and Q3 cannot provide the fast current spikes necessary to quickly (and therefore efficiently) pull up or down Q4's gate capacitance. In addition, the level shifter current ILS set by R4 must be high enough to shift the gate charge QGate of Q4 during ton (min). That is:

Capacitor C4 is set larger than the gate capacitance of Q4, but must be small enough to be recharged during the shorter controller minimum on and off times. Figure 3 shows the gate and drain on/off times for one switching cycle at 300V and 500mA load input voltage. Table 1 shows the measured conversion efficiency.

Figure 3. Gate and drain voltages of Q4 during one switching cycle

Table 1 Measured conversion efficiency:

Current Limit and Soft-Start

In many low-voltage applications, the TPS6420x uses a high-side current-limiting circuit designed to compare the voltage drop across a current-sense resistor installed between the VIN and ISENSE pins to a reference voltage. If the voltage across the sense resistor exceeds this voltage, the circuit turns off the switch, thereby achieving pulse-by-pulse current limiting. In high-voltage applications, the current-limiting circuit cannot be used without an overvoltage on the ISENSE pin, so the ISENSE pin is tied high to VIN. The circuit shown in Figure 1 does not have current limiting, and a high-side fuse is recommended for short-circuit protection.

In some typical startup applications, the TPS64203 current limit value rises slowly to provide a controlled soft start with current limit. In this application, both the current limit circuit and the soft start are ineffective; therefore, the startup inrush current will be large and the output voltage will overshoot slightly, as shown in Figure 4.

Figure 4 10Ω load startup at VIN=300V

in conclusion

Using a level shifter and gate driver and a local power supply can be achieved using a low voltage buck converter to provide a DC voltage from the AC power supply, using a simple circuit without a transformer to obtain nearly 60% conversion efficiency. This circuit can also be used for DC/DC conversion, where the input DC voltage is higher than the maximum rating of the TPS6420x.

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