Practical Tips | Why does Ka-band need more bandwidth?

Latest update time：2021-01-29

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As the demand for global connectivity grows, many satellite communication (satcom) systems are increasingly using Ka-band frequencies, and the requirements for data rates are also rising. Currently, high-performance signal chains can support multi-gigabit instantaneous bandwidth, and there may be hundreds or thousands of transceivers in a system, making ultra-high throughput data rates a reality.

In addition, many systems have begun to move from mechanically positioned static parabolic antennas to active phased array antennas. Driven by enhanced technology and higher levels of integration, component size has been greatly reduced to meet the needs of the Ka band. Phased array technology can also improve interference reduction performance by forming nulls in the antenna radiation pattern along the direction of the interfering signal.

The following will briefly describe some of the trade-offs that exist in existing transceiver architectures and the suitability of different types of architectures for different types of systems. This analysis will break down some of the key specifications for satellite systems and how these system-level specifications lead to the specifications for the components at the transceiver signal chain level.

Break down technical specifications from system-level analysis down

At a macro level, satellite communication systems need to maintain a certain carrier-to-noise ratio (CNR), which is the result of the link budget calculation. Maintaining this CNR guarantees a certain bit error rate (BER). The required CNR depends on many factors, such as error correction, information coding, bandwidth, and modulation type. Once the CNR requirement is determined, the technical specifications of each receiver and transmitter can be broken down based on the high-level system requirements. Generally, the first thing to obtain is the gain-system noise temperature (G/T) figure of merit of the transceiver and the effective isotropic radiated power (EIRP) of the transmitter.

For the receiver, to derive the low-level receiver signal chain specifications from G/T, the system designer needs to know the antenna gain and the system noise temperature, which is a function of the antenna pointing and the receiver noise temperature, as shown in Equation 1. Based on this, the receiver temperature can be derived using Equation 2.

The noise figure of the receiver signal chain can then be calculated using Equation 3:

Once the receiver noise figure is known, a cascade analysis can be performed to ensure that the signal chain meets these necessary specifications and whether adjustments need to be made.

For the receiver, first determine the required EIRP based on the distance of the receiver (ground to satellite or satellite to ground) and the receiver sensitivity. Once the EIRP requirement is known, a trade-off needs to be made between the output power of the transmit signal chain and the antenna gain. For a high-gain antenna, the power consumption and size of the transmitter can be reduced, but at the expense of increasing the antenna size. EIRP is calculated using Equation 4.

With careful selection of components used in the signal chain, output power can be maintained without degrading other important parameters such as output noise and out-of-band RF energy that could interfere with other systems.

Other important transmitter and receiver specifications include:

Instantaneous bandwidth: The bandwidth of the spectrum that the signal chain can digitize at any point in time

Power handling: The maximum signal power that the signal chain can handle without performance degradation

Phase coherence between channels: For emerging beamforming systems, ensuring predictable phase between channels can simplify the processing and calibration of beamforming signals.

Spurious performance: Ensures that receivers and transmitters do not generate RF energy at undesired frequencies that could affect the performance of that or other systems

Figure 1. Architecture comparison: (a) high IF (integrated TRx), (b) double-conversion superheterodyne architecture (with GSPS ADC)

It is important to keep these and other specifications in mind during the design of the signal chain to ensure a high-performance system that meets the needs of any given application, whether it is a wideband multi-carrier aggregation hub or a single narrowband handheld satellite communications terminal.

General Architecture Comparison

Once the high-level specifications are determined, the decision on which signal chain architecture to use can be made. One key specification listed earlier that can have a significant impact on the architecture is instantaneous bandwidth. This specification affects both the analog-to-digital converter (ADC) at the receiver and the digital-to-analog converter (DAC) at the transmitter. To achieve high instantaneous bandwidth, the data converter must be sampled at a higher rate, which generally drives up the power consumption of the entire signal chain, but when viewed on a per-watt basis (W/GHz), it reduces power consumption.

For systems with bandwidths less than 100 MHz, a basic architecture similar to that shown in Figure 1a is often preferred. This architecture combines a standard down-conversion stage with an integrated direct-conversion transceiver chip. The integrated transceiver allows for very high levels of integration, which significantly reduces size and power consumption.

To achieve bandwidths up to 1.5 GHz, the classic double-conversion superheterodyne architecture can be combined with state-of-the-art ADC technology; this is shown in Figure 1b. This is a mature, high-performance architecture with integrated frequency conversion stages to filter out unwanted spurious signals. Depending on the received frequency band, a downconversion stage is used to convert the received signal to an intermediate frequency (IF), and another downconversion stage is used to convert the final IF signal to a lower frequency that the ADC can digitize. The lower the final IF, the higher the ADC performance, but at the expense of increased filtering requirements. Generally, this architecture is the largest and most power-hungry of the four options presented in this article, due to the increased component count.

A similar option is shown in Figure 1c, which shows a single conversion stage to convert the signal to an IF that is sampled by a GSPS ADC. This architecture takes advantage of more of the RF bandwidth that the ADC can digitize with little performance degradation. The latest GSPS ADCs on the market can directly sample RF frequencies up to 9 GHz. In this option, the IF is centered between 4 GHz and 5 GHz, which provides the best balance between signal chain filtering requirements and ADC requirements.

The final option is shown in Figure 1d. This architecture provides an even greater increase in instantaneous bandwidth, but at the expense of significant complexity and potential performance degradation. This is a direct conversion architecture that uses a passive I/Q mixer that outputs two IFs at baseband that are offset by 90°. Each I and Q path is then digitized using a dual GSPS ADC. In this case, up to 3 GHz of instantaneous bandwidth can be achieved. The main challenge with this option is maintaining quadrature balance between the I and Q paths as the signal propagates through the mixer, low-pass filter, and ADC driver. Depending on the specific CNR requirements, this tradeoff may be acceptable.

This is a brief high-level overview of how these receiver architectures work. This list is not exhaustive and combinations of options can be used. Although the comparison does not include the transmit signal chain, each option in Figure 1 has a corresponding transmit signal chain with similar tradeoffs.

Ka-band satellite communications receiver example

Now that we have discussed the advantages and disadvantages of various architectures, we can apply this knowledge to real signal chain examples. Currently, many satellite communication systems operate in the Ka band to reduce antenna size and increase data rates. This is especially important in high-throughput satellite systems. Below are examples of different architectures that we will compare in more detail.

For systems requiring instantaneous bandwidths below 100 MHz, such as very small aperture terminals (VSAT), an IF architecture with an integrated transceiver chip (AD9371) can be used, as shown in Figure 2. This design achieves a low noise figure and has the smallest design size due to its high level of integration. Its performance is summarized in Table 1.

Figure 2. High IF (integrated TRx) with bandwidth up to 100 MHz

As a hub for multiple users of satellite communication systems, these systems may have to process multiple carrier signals simultaneously. In this case, the bandwidth or bandwidth/power of each receiver becomes very important. The signal chain shown in Figure 3 uses a high speed ADC, the AD9208, which is a recently released high sampling rate ADC that can digitize instantaneous bandwidths up to 1.5 GHz. In this example, to achieve an instantaneous bandwidth of 1 GHz, the IF is placed at 4.5 GHz. The bandwidth achievable here depends on the filtering requirements of the anti-aliasing filter placed before the ADC, but is generally limited to ~75% of the Nyquist zone (half the sampling rate).

Figure 3. Single downconversion to high IF using a GSPS ADC.

In systems where the highest instantaneous bandwidth is required, possibly at the expense of CNR, the signal chain shown in Figure 4 can be used. This signal chain uses an I/Q mixer, the HMC8191, which has an image rejection performance of ~25 dBc. In this case, the image rejection performance is limited by the amplitude and phase balance between the I and Q output channels. This is the limiting factor of this signal chain without the use of more advanced quadrature error correction (QEC) techniques. The performance of this signal chain is summarized in Table 1. Note that the NF and IP3 performance are similar to the other options, but the power/GHz specification is the lowest of the three, and the size is also the best in terms of the amount of bandwidth that can be utilized at any time.

Figure 4. Direct frequency conversion using an I/Q mixer and a GSPS ADC.

The three receive options presented here are shown in the table below, but it is important to note that this table is not an exhaustive list of possible options. The summary here is intended to show the differences between the various signal chain options. In any given system, the final optimal signal chain may be one of the three or a combination of any of the options.

Also, although only the receiver side is shown in the table, similar tradeoffs exist in the transmitter signal chain. Typically, when a system moves from a superheterodyne architecture to a direct conversion architecture, a tradeoff is made between bandwidth and performance.

Data interface

After the data is digitized by the ADC or transceiver, it must be fed to the system through a digital interface. All of the data converters mentioned here use the high-speed JESD204b standard to receive the signal from the data converter, package it into a frame, and transmit it over a small number of traces. The data rate of the chip varies depending on the system requirements, but all of the devices mentioned here have digital functions for decimation and frequency conversion to adapt to different data rates to meet different system requirements. The specification supports rates up to 12.5 GSPS on the JESD204b lane, which is fully utilized by high-bandwidth systems that transmit large amounts of data. A detailed description of these interfaces can be found in the AD9208 and AD9371 data sheets. In addition, the choice of FPGA must take this interface into consideration. Many FPGAs from vendors such as Xilinx® and Altera® now have this standard integrated into their devices, facilitating integration with these data converters.

in conclusion

This article details the various tradeoffs and provides examples of signal chains that are appropriate for Ka-band satellite communications systems. Several architectural options are presented, including a high IF single-conversion option that utilizes the AD9371 integrated transceiver, a similar architecture that replaces the integrated transceiver with a GSPS ADC to increase instantaneous bandwidth, and a direct conversion architecture that increases bandwidth but degrades image rejection. The signal chains presented can be used as is, but it is recommended that you build on them as a basis for your design. Depending on the specific system-level application, different requirements will arise, and the choice of signal chain will become clearer as the design progresses.

Source: ADI Author: Brad Hall

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