How to build AC and DC data acquisition signal chains? This method is easy and effective~

This article also compares continuous-time converters to discrete-time converters and highlights the system advantages and limitations of using continuous-time Σ-Δ ADCs.

Data digitization includes two basic processes: sampling and quantization, as shown in Figure 1. Sampling is the first step, in which the continuous-time variable analog signal x(t) is converted into a discrete-time signal x(n) using the sampling frequency f _S. The final result is a signal with an interval of 1/T _S (f _S = 1/T _S ).

Figure 1. Data sampling.

The second step is quantization, which estimates these discrete time sample values ​​to a finite set of possible values ​​and represents them with a digital code, as shown in Figure 1. This quantization operation to a finite set of values ​​causes digitization errors, called quantization noise.

The sampling process also causes aliasing, which can be seen as folding back of the input signal and harmonics around the sample and hold clock frequency. The Nyquist criterion requires that the sampling frequency must be at least twice the highest signal frequency. If the sampling frequency is less than twice the maximum analog signal frequency, a phenomenon called "aliasing" will occur.

To understand what aliasing means in the time and frequency domains, first consider the time domain representation of a sampled single-tone sine wave signal, shown in Figure 2. In this case, the sampling frequency, f _{S ,} is not at least twice fa , but is only slightly higher than the analog input frequency, fa _{, and} therefore does not meet the Nyquist criterion. Note that the actual sample pattern would produce an aliased sine wave of a lower frequency, f _S – _{fa .}

Figure 2. Aliasing: time domain representation.

Figure 3. Aliasing: frequency domain representation.

The corresponding frequency domain representation of this situation is shown in Figure 3.

The Nyquist bandwidth is defined as the spectrum from DC to f _S /2. This spectrum can be subdivided into an infinite number of Nyquist zones, each with a width of 0.5 f _S . In practical applications, the ideal sampler can be replaced by an ADC followed by an FFT processor. The FFT processor only provides outputs in the range of DC to f _S /2; that is, signals or aliases that appear in the first Nyquist zone.

If an ideal pulse sampler is used, a single-frequency sine wave of frequency f _a is sampled at frequency f _{S (see Figure 1). Also assume that f S} > 2f _a . The frequency domain output of the sampler shows that there are aliases or images of the original signal at every multiple of f _{S ; that is, at frequencies |± Kf S} ± f _a |, K = 1, 2, 3, 4, etc.

Next, let’s consider a signal outside the first Nyquist zone (Figure 3). The signal frequency is only slightly less than the sampling frequency, which is what we see in the time domain in Figure 2. Note that even though the signal is outside the first Nyquist zone, its image (or alias) f _S – _fa is still within the zone. Returning to Figure 3. Clearly, if an interfering signal is present at any of the image frequencies fa, it will also appear at fa _{, thus} creating a spurious frequency component within the first Nyquist zone.

For high-performance applications, system designers need to address quantization noise, aliasing, and switched-capacitor input sampling issues caused by the sampling process. Two types of precision ADCs are built using switched-capacitor based sampling techniques, the successive approximation register (SAR) and Σ-Δ ADCs that are common in the industry.

In an ideal Nyquist ADC, the LSB size of the ADC will determine the quantization noise introduced to the input when performing the analog-to-digital conversion. This quantization noise is distributed over a bandwidth of f _S /2. To address the quantization noise issue, the first technique is to use oversampling, which is to sample the input signal at a rate significantly higher than the Nyquist frequency to improve the signal-to-noise ratio (SNR) and resolution (ENOB). During oversampling, the sampling frequency is chosen to be N times the Nyquist frequency (2 × f _IN ), so the same quantization noise must be distributed over a range of N times the Nyquist frequency. This also relaxes the requirements of the antialiasing filter. The oversampling ratio (OSR) is defined as f _S /2f _IN , where f _IN is the signal bandwidth of interest. Generally speaking, oversampling the ADC by 4 times provides an additional 1 bit of resolution, or 6 dB of additional dynamic range. Increasing the oversampling ratio reduces the overall noise and increases the dynamic range (DR) because oversampling is ΔDR = 10log10 OSR in dB.

Oversampling can be used and implemented with integrated digital filters and decimation. The basic oversampling modulator of a delta-sigma ADC shapes the quantization noise so that most of it appears outside the bandwidth of interest, thereby increasing the overall dynamic range at low frequencies, as shown in Figure 4. A digital low-pass filter (LPF) then removes the quantization noise outside the bandwidth of interest, and the decimator reduces the output data rate back to the Nyquist rate.

Figure 4. Oversampling example.

Noise shaping is another technique used to reduce quantization noise. In a sigma-delta ADC, a low-resolution (one-bit to five-bit) quantizer is used within the loop after the loop filter. The DAC is used as feedback to extract the quantized signal from the input, as shown in Figure 5.

Figure 5. Noise shaping.

The integrator accumulates the quantization error and shapes the quantization noise to a higher frequency, which is then filtered using a digital filter. Figure 6 shows the power spectral density (PSD) of a typical Σ-Δ ADC output x[n]. The noise shaping slope depends on the order of the loop filter, H(z) (see Figure 11) and is (20 × n) dB per decade, where n is the order of the loop filter. Σ-Δ ADCs achieve high in-band resolution by combining noise shaping with oversampling. The in-band bandwidth is equal to f _ODR /2 (ODR is the output data rate). Higher resolution can be achieved by increasing the order of the loop filter or increasing the oversampling ratio.

Figure 6. Oversampling and noise shaping diagram.

To address aliasing in high performance applications, a higher order anti-aliasing filter can be used to avoid any amount of aliasing. The anti-aliasing filter is a low-pass filter that bandwidth limits the input signal and ensures that the signal does not contain frequency components outside the bandwidth of interest that can fold back. The filter performance will depend on how close the out-of-band signal is to f _S /2 and the amount of attenuation required.

For SAR ADCs, the difference between the input signal bandwidth and the sampling frequency is not that large, so we need to use a higher order filter, which requires a more complex, higher order filter design with higher power and distortion. For example, if the input bandwidth of a SAR sampling at 200 kSPS is 100 kHz, the anti-aliasing filter needs to reject input signals >100 kHz to ensure that no aliasing occurs. This requires the use of a very high order filter. Figure 7 shows the steep requirement curve.

Figure 7. Aliasing requirements.

If you choose to use a 400 kSPS sampling speed to reduce the filter order, you will need to reject input frequencies >300 kHz. Increasing the sampling speed increases power, and if you double the speed, you double the power required. Since the sampling frequency is much higher than the input bandwidth, further increasing the oversampling at the expense of power will further relax the antialiasing filter requirements.

In a Σ-Δ ADC, oversampling the input with a higher OSR relaxes the antialiasing filter requirements since the sampling frequency is much higher than the input bandwidth, as shown in Figure 8.

Figure 8. Antialiasing filter requirements in a sigma-delta architecture.

Figure 9 shows the complexity of the AAF in both the SAR and discrete-time Σ-Δ (DTSD) architectures. If we want to achieve 102 dB attenuation at sampling frequency f _S using a 100 kHz –3 dB input bandwidth , the DTSD ADC will require a second-order antialiasing filter, whereas a fifth-order filter is required to achieve the same attenuation at f _S with a SAR ADC .

For the continuous time Σ-Δ (CTSD) ADC, it has its own attenuation function, so we do not need to use any anti-aliasing filter.

Figure 9. AAF filter requirements for various architectures.

These filters present challenges to system designers, who must optimize them to provide attenuation within the frequency band of interest and as high a rejection as possible. They also add many other errors such as offset, gain, phase error, and system noise, which degrade their performance.

Furthermore, high performance ADCs are inherently differential, so we need to use double the number of passive components. To achieve better phase matching in multichannel applications, all components in the signal chain must also be matched. Therefore, tighter tolerance components are required.

Switched capacitor input sampling depends on the settling time of the sampled input on the capacitor, so when the sampling switch is turned on and off, a charging/discharging transient current is required. This is called input kickback and requires an input driver amplifier that can support these transient currents. In addition, the requirement that the input settle by the end of the sampling time and the accuracy of the sampled input determines the performance of the ADC, which means that the driver amplifier needs to settle quickly and steadily after the kickback event. Therefore, a high bandwidth driver that supports fast settling and can absorb the kickback of the switched capacitor operation is required. In switched capacitor inputs, the driver must immediately provide power to the holding capacitor whenever sampling is turned on. This current surge can only be provided in time if the driver has sufficient bandwidth capability. Kickback occurs on the driver when sampling due to switching parasitics. If the kickback does not settle before the next sample, it will cause sampling errors and affect the ADC input.

Figure 10. Sampling kickback.

Figure 10 shows the kickback on the DTSD ADC. For example, if the sampling frequency is 24 MHz, then the data signal needs to settle in 41 ns. Because the reference is also a switched capacitor input, a high bandwidth buffer is also required on the reference input pin. These input signal and reference voltage buffers also add noise, degrading the overall performance of the signal chain. In addition, the distortion components of the input signal driver (around the S&H frequency) further increase the anti-aliasing requirements. For switched capacitor inputs, changes in sampling speed will cause changes in input current. This may cause re-tuning of the system to reduce the gain error generated by the driver or the previous stage when driving the ADC.

The CTSD ADC is another Σ-Δ ADC architecture that utilizes principles such as oversampling and noise shaping, but provides an alternative method of implementing sampling with significant system advantages.

Figure 11 compares the DTSD and CTSD architectures. As can be seen, the DTSD architecture samples the input before the loop. The loop filter H(z) is discrete in time and implemented using a switched capacitor integrator. The feedback DAC is also based on switched capacitors. Since sampling the input will cause aliasing issues in fS, an anti-aliasing filter is required at the input before sampling the input.

Figure 11. Discrete-time and continuous-time modulator block diagrams.

The CTSD does not have a sampler at the input, but rather samples at the quantizer inside the loop. The loop filter is made continuous in time using a continuous time integrator, as is the feedback DAC. Just as the quantization noise is shaped, so is the aliasing due to sampling. This results in an ADC that is virtually free of sampling aliasing, making it in a class of its own.

The sampling frequency of CTSD is fixed, unlike DTSD where the modulator sampling frequency can be easily extended. In addition, CTSD ADCs are less tolerant to jitter than switched capacitor ADCs. An off-the-shelf crystal or CMOS oscillator provides a local low-jitter clock to the ADC, which helps avoid transmitting a low-jitter clock across isolation and reduces EMC.

The CTSD has two major advantages. It has inherent alias rejection and provides resistive inputs for both the signal and the reference.

Moving the quantizer inside the loop creates inherent alias rejection. As shown in Figure 12, the input signal passes through the loop filter before sampling, and the foldback (aliasing) error generated at the quantizer is also removed by this filter. The signal and aliasing error have the same noise transfer function as the sigma-delta loop, and similar noise shaping as the quantization noise is implemented in the sigma-delta architecture. Therefore, the frequency response of the CTSD loop naturally rejects input signals that are approximately integer multiples of the sampling frequency, acting as an anti-aliasing filter.

Figure 12. Frequency response of the CTSD modulator.

Having resistive inputs in both the signal and reference inputs is much easier to drive than a sample-and-hold configuration. When a constant resistive input is provided, there is no kickback and the driver can be removed completely. No distortion is introduced to the input, as shown in Figure 13. And because the input impedance is constant, there is no need to re-tune the system due to gain errors.

Figure 13. Input setup for CTSD.

Even if the ADC has unipolar supplies, the analog inputs may be bipolar. Therefore, there is no need to implement level translation between the bipolar front end and the ADC. The dc performance of the ADC may be different than it would be if the input resistors now had input common-mode related currents and input currents.

The reference load is also resistive to reduce switching kickback, thus eliminating the need for a separate reference buffer. The resistors for the low-pass filter can be on-chip so that they track with the on-chip resistive load (since they are likely to be the same material) to reduce gain error temperature drift.

The CTSD architecture is not new, but the megatrend in the industrial and instrumentation markets requires DC and AC precision performance at higher bandwidths. In addition, customers prefer a single platform design for most solutions to help them reduce time to market.

The CTSD architecture offers several advantages over other types of ADCs, making it the preferred choice for many applications such as high-performance audio and cellular handset RF front ends. These advantages include easier integration and lower power consumption, but more importantly, the use of CTSDs can solve several important system problems. Due to a number of technical limitations, the use of CTSDs has previously been limited to audio/bandwidth and lower dynamic range. Therefore, the mainstream solution for high-precision, high-performance/medium bandwidth applications has been high-performance Nyquist rate converters such as successive approximation ADCs and oversampled DTSD converters.

However, recent technology breakthroughs from Analog Devices have overcome many of these previous limitations. The AD7134 is the first high-precision CTSD-based dc to 400 kHz bandwidth ADC that can achieve higher performance specifications while providing dc accuracy, thereby addressing several key system-level issues in high-performance instrumentation applications. The AD7134 also integrates an asynchronous sample rate converter (ASRC) that can provide data at different data rates from the fixed sampling speed of the CTSD. The output data rate can be independent of the modulator sampling frequency and can ensure that different granularities of throughput can be successfully used with the CTSD ADC. The output data rate can also be flexibly changed at the granularity level, allowing users to use coherent sampling.

The inherent aliasing suppression eliminates the need for anti-aliasing filters, thereby reducing component count and making the solution size smaller. More importantly, the performance issues associated with anti-aliasing filters, such as droop, offset, gain error, phase error, and noise in the system, are no longer present.

Anti-aliasing filters can significantly increase the overall delay of the signal chain depending on the rejection requirements. Removing the filter can completely eliminate this delay and enable precision conversion in noisy digital control loop applications.

No anti-aliasing filter is required at the system level, which greatly improves the phase matching performance of multi-channel systems. It is very suitable for applications that require low mismatch between channels, such as vibration monitoring, power measurement, data acquisition modules and sonar.

Because of the inherent filtering function, the CTSD ADC is not affected by any system-level interference or IC internal interference. For the DTSD ADC and SAR ADC, attention must be paid to reducing the interference during ADC sampling. In addition, because of the inherent filtering function, the power supply line will not be interfered.

With constant resistive analog and reference inputs, dedicated drivers are completely eliminated. In addition, all performance-related issues such as offset, gain, phase error, and system noise errors no longer exist.

Because the number of design components is greatly reduced, it is much easier to achieve precision performance, which can shorten design time, speed up product launch, simplify BOM management, and improve reliability.

The system board size is significantly reduced by eliminating the need for anti-aliasing filters, drivers, and reference buffers. An instrumentation amplifier can be used to directly drive the ADC. For the AD7134, since it is only a differential input ADC, a differential instrumentation amplifier (such as the LTC6373) can be used as a driver. A discrete-time signal chain and a continuous-time signal chain are compared in Figure 14. Experimental results show that the continuous-time signal chain can save 70% of the area compared to the equivalent discrete-time signal chain, making it ideal for high-density multichannel applications.

Figure 14. Comparison of discrete-time (left) and continuous-time (right) signal chains.

Figure 15. Discrete-time signal chain and continuous-time signal chain size comparison.

In summary, the AD7134 allows for easy design-in, significantly reduces system size, simplifies signal chain design, improves system reliability, and shortens overall time to market without compromising performance parameters required for precision instrumentation applications.