Cadence LPDDR4/4X memory IP subsystem passes ISO 26262 ASIL C certification

“High-performance memory subsystems are essential elements for ADAS and autonomous driving applications and must be tailored to meet more stringent requirements,” said Wolfgang Ruf, semiconductor product manager at SGS-TÜVSaar. “After rigorous evaluation, Cadence LPDDR4/4X PHY and control The processor subsystem has been officially certified by SGS-TÜVSaar, complies with the ISO 26262 standard, and has met the ASIL C application requirements. SoC designers can use this high-performance subsystem as a key design element of the ASIL C system.”

“Cadence’s automotive-grade LPDDR4/4X design IP has been silicon verified in TSMC’s 16FFC FinFET automotive-grade process,” said Suk Lee, senior director of design infrastructure marketing at TSMC. “Subsystems integrating Cadence controllers and PHY have been implemented in TSMC’s The 16FFC automotive-grade standard cell library has been verified, which ensures higher SOC performance, more robust verification results, better interactivity and shorter time to market. TSMC’s 16FFC automotive-grade process technology remains advanced automotive. The preferred process for applications including ADAS and autonomous driving chips where ISO 26262 ASIL C readiness is a key requirement for processor and memory subsystem functionality.”

"For advanced SoCs used in ADAS, autonomous driving and other automotive systems, processors and memory subsystems are critical, and their functional safety requirements are more stringent," said Cadence Global Vice President of R&D and IP Design Group Amjad Qureshi said, "We have worked closely with our automotive customers, SGS-TÜVSaar and TSMC to complete the functional safety analysis and audit process to achieve ISO 26262 ASIL C-ready certification. Customers can now use our high-performance LPDDR PHY and control with confidence "