Parasitic extraction and static timing analysis of 3D-IC design
Authors of this article: Zhang Qianyi, Shen Long
Cadence Corporation DSG Product Engineering Group
Advanced manufacturing processes allow design engineers to break through the limits of chip performance, power consumption and area again and again. In order to continue the pursuit of faster speeds, stronger functions, and lower costs, the Moores are still tirelessly looking for new methods. 3D-IC is one of them: through the update of packaging and interconnection technology, multiple dies can be integrated into the same chip (chip) , so that the high-speed interconnection on the chip replaces the previous low-speed interconnection outside the chip. . This new dimension creates unlimited possibilities for improving the performance of future chips. Since May this year (see previous issues at the end of this article) we have revealed in detail how the Cadence system platform can help 3D designers for five consecutive issues. Now let’s take a look at what challenges the new interconnect methods and process integration involved bring to parasitic parameters and timing analysis, and how we can prepare chip signoff personnel in advance.
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How to extract uBUMP and TSV parasitics
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Do coupling capacitances between interposers need to be considered urgently?
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Integration and expansion of static timing analysis
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How to deal with the explosive growth of PVT analysis corners
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design example
01
How to extract uBUMP and TSV parasitics
First, let’s introduce what uBUMP and TSV are .
uBUMP is usually used to connect the upper and lower die stacks and needs to be defined with an IPF (Inter-Process-File) file. A via (VIA) is defined between two adjacent wiring layers. TSV (Through Silicon Via) refers to the through hole defined in the 3D-IC process that connects the first layer of metal on the back and the first layer on the front. There is also a Long TSV , which refers to a through hole connecting the first layer of metal on the back and a layer of metal above the first layer on the front.
Quantus has two calculation methods for uBUMP and TSV when extracting parasitic parameters . One is usually described by model statements in the ICT file, and the other is by defining an additional TSV model file (.subckt) for annotation when extracting the overall parasitic parameters. Currently, Quantus can support the extraction of resistance and ground capacitance using TSV model statements. These resistance and capacitance values are written in the output netlist just like ordinary parasitic parameter extraction.
02
Do coupling capacitances between interposers need to be considered urgently?
Basic 3D-IC parasitic parameter extraction includes TSV, uBUMP and the extraction of the metal layer on the back of the chip. However, with the advancement of technology, the distance between the two DIEs has become closer, so the capacitance between the two windings cannot be ignored. Quantus now supports IDX capacitor extraction. IDX is a new coupling capacitance formed between two DIEs in 3D-IC. The coupling capacitance between two DIEs can be used to perform more accurate system-level static timing analysis. The two DIEs can be of the same or different manufacturing processes. IDX parasitic extraction supports iHDB input in Cadence Integrated 3D-IC , and the output results can be stored in iHDB for subsequent Tempus timing analysis.
03
Integration and expansion of static timing analysis
静态时序分析（STA）一直是芯片签核工程师关注的重点。 Integrity 3D-IC 平台自然是不能少了 STA 的功能集成。除了命令行和脚本的输入，平台的用户界面也添加了用户交互界面的支持，比如一直很受 Tempus 和 Innovus 使用者喜爱的 Global Timing Debug （GTD） ，该功能可以协助分析关键路径的时序违例原因。
如下图所示， STA 产生报告之后， GTD 为设计工程师显示 Path Histogram、Path Layout、Hierarchy、Slack Calculation 和其他许多很有价值的分析报告和视图。具体使用描述详见 Cadence support 官网上的 Global Timing Debug（GTD）using Tempus or Innovus, version 18.1（cadence.com） （请扫描下方二维码登录 Cadence Support 查看）
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芯片的复杂度可以无限增加了，设计规模自然也随之上升。当 flatten 的全芯片分析时间过长或者内存用量过大时，就需要考虑通过抽取简化模型进行层次化时序分析。在 Tempus 里这一解决方案叫做边界模型 （Boundary Mode） 。如下图左所示这个模型去除了 block 内部 reg->reg 的 path 仅保留 block 对外互联以及相关联的部分，包括：
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所有的 input ports 的 fan-out 逻辑和 output ports 的 fan-in 逻辑
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所有对保留逻辑有 SI 影响的电路
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所有保留逻辑的边负荷电路 （side load）
通过对每个 die 做 Boundary Model 的抽取，整体网表的缩减率可以达到 90%，而 setup slack 的平均差异控制在 0.1ps，99.73% 的路径在 2.7ps 以内。
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如何应对PVT分析corner的爆炸式增长
从性能的角度上来看，3D-IC 一个很强大的功能就是支持了本地的、高速的 Die 之间的同步通讯。然而这一新功能也给静态时序签核（STA）增加了大量的分析 corner。现今的设计只有一个 Die 在做全局 STA，每条时序路径都是在一组给定的 PVT 参数下做分析。在 3D-IC 设计中，多个 Die 是同时工作在不同的 PVT 参数下。设想当你有一条同步的时序路径从 Bottom Die 开始出发（startpoint），经过 Middle Die，最后抵达 Top Die（endpoint），这条 path 就会经历三种不同的 PVT 条件，好像我们从北半球旅行到南半球会穿越不同地理环境和气候。
因为 3D 设计允许每个 Die 可以有独自的 PVT corner ，这样 STA 签核就必须涵盖所有的可能出现的组合情况。以上图里三个 Die 的典型设计为例，如果 Die1 和 Die2 的 process corner 都是 12 个， Die3 是 6 个；三个 Die 的 Voltage corner 和 Temperature corner 都只考虑 2 个相同的，那么总共需要分析的 corner 数量就已经达到 （12x12x6）x 2 x 2 = 3456 个。
针对这个 3D 设计中 corner 爆炸式增长的挑战， Tempus 开发了一个新的 Rapid Automated Inter-Die（RAID） 技术，可以在分析这些 feed through paths 时巧妙地大量缩减 corner 数量，同时保证计算精度。下图是一个非常简化的 3 层 Die 的例子，假设每层都只有 3 个 corner（N=K=M=3） ，那么全组合需要分析的 corner 数量就是 27 个（N*K*M） 。 Feed through 的部分通过 represent delay 和 adjustment 替换， K 最大就可以 reduce 到 1，这样在这个 case 里 corner 就减小到了 9 个， corner 的缩减率是 3X 。对于中间 Die 超过 10 个 corner 的设计， reduction ratio 将会超过 10X ；对于更多层堆叠的 3D 设计，缩减率就更为可观！
For general path analysis without feed through, the number of corners will not increase so much, but the demand for machines will still increase as the complexity of the design increases. Cadence's other existing powerful parallel analysis engine concurrent multi-mode multi-corner (C-MMMC) provides a second-dimensional solution for this. This function efficiently reuses the same DB data of multiple corners, stores intermediate data that effectively reduces the amount of calculations, and improves the parallel usage of the CPU, thereby significantly reducing the usage requirements for machines and hard disks. For STA analysis of the same delay corner and different constraint corners, the increase in running time and memory usage is only about 20%. Compared with serial analysis, the runtime reduction of CMMMC can usually reach 4-5X.
05
design example
Finally, let us look at an actual 5nm 3D design case. The design includes a logic die with 6 process corners, and 2 SRAM dies with 12 process corners respectively. If traditional STA analysis is used, it will take 8-9 days to complete the combined analysis of all 864 (6*12*12) process corners even in CMMMC mode (multi-threading uses 32 CPUs, @2.6GHZ frequency). After using Boundary Model technology, the time can be greatly shortened to 15 hours; after continuing to use RAID technology, the number of sign-off corners is reduced to 144, and it only takes an astonishing 4 hours and 27 minutes to complete the same timing analysis! Adding in the maximum time required to generate a Boundary Model (6 hours and 50 minutes), the speed improvement is still close to 40X!
The Cadence Integrity 3D-IC platform is the industry's first comprehensive overall 3D-IC design planning, implementation and analysis platform. The platform integrates Cadence's multiple powerful analysis tools and optimization engines from a system-wide perspective to comprehensively evaluate and optimize the chip's performance, power consumption, heat dissipation and area. Among them, the parasitic parameter extraction tool Quantus accurately calculates the resistance and capacitance effects between 3D vias and mid-layers; the static timing analysis tool Tempus greatly improves the efficiency of multi-process combination STA analysis, reducing the analysis speed that previously required weekly records to hours. . Powerful and accurate computing power supports 3D-IC applications such as high-bandwidth and high-data throughput machine learning, high-performance storage devices, and cloud computing.
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