In high-power scenarios such as photovoltaic and wind power generation, power devices need to carry extremely high currents. However, power semiconductor manufacturers usually do not produce devices with larger rated currents because of the low production yield of large-size chips, insufficient market demand, and the large package size of large-current chips, which can easily lead to increased package warpage. A common method in the industry is to connect multiple devices with smaller rated currents in parallel, which can not only meet the needs of large currents, but also reduce conduction losses, improve efficiency, and expand current capacity.

However, in the actual application of parallel design, problems such as uneven current during conduction, uneven current during switching, and chip gate oscillation often occur.

During the conduction process of parallel power devices, ensuring uniform current distribution is a key consideration, and this process is often interfered by various factors, resulting in uneven current distribution. The primary factor is the inconsistency of Vce(sat) and RDS(on) between devices in the on state . When some devices exhibit lower Vce(sat) or RDS(on), they naturally tend to carry more current, thus breaking the ideal current sharing state. Secondly, the difference in threshold voltage (Vgs(e)th) will also lead to uneven current distribution . Devices with smaller Vgs(e)th also have smaller on-resistance (RDS(on)), which further aggravates the imbalance of current distribution. In addition, the temperature characteristics of the device cannot be ignored. The negative temperature coefficient may cause more uneven current distribution when the temperature rises, while the positive temperature coefficient helps to improve the current sharing effect.

To effectively solve the problem of static current sharing, we need to consider two aspects: device selection and system design.

First, in terms of device selection, it is recommended to screen the on-resistance at the nominal operating current to ensure impedance matching between parallel devices, thereby achieving more uniform current distribution. It is recommended to give priority to power devices with consistent or similar Vce(sat) and RDS(on) parameters, ensuring that the differences in these device parameters are controlled within 0.1V and 5%, respectively.

Secondly, the difference in Vgs(e)th parameters of different devices should be controlled below 0.1V. Finally, using power semiconductor devices with positive temperature coefficient (PTC) is a wise move to improve the current sharing effect, because the PTC characteristic enables the device to automatically adjust the current distribution as the temperature rises, which is conducive to balancing. However, if the application scenario requires a low switching frequency and considers using an IGBT with a negative temperature coefficient (NTC) to optimize the conduction loss, it is necessary to ensure that the operating current exceeds the turning point of the NTC to avoid the current imbalance caused by temperature.

During the switching phase of power semiconductor devices, the problem of dynamic current imbalance is particularly prominent. This phenomenon is partly attributed to the inconsistency between devices in key parameters, such as V _TH , Miller platform voltage (V _plateau ) and input capacitance (C _ies ). Devices with low VTH will turn on earlier due to their lower threshold voltage, and due to their smaller C _ies and gate-emitter capacitance (C _ge ), they charge faster, causing these devices to bear greater energy losses (Eon and Eoff) during switching operations. This concentration of energy loss will cause the junction temperature (TJ) of the device to increase, which may in turn reduce V _TH , causing these devices to turn on earlier in subsequent switching operations, forming a current concentration cycle, exacerbating current imbalance.

Secondly, larger source inductance and impedance will cause the device to turn on slowly and turn off later . Specifically, smaller source stray inductance (LS) will cause the device to bear larger energy loss (Eon) when it is turned on, while larger source stray inductance will cause the device to bear larger energy loss (Eoff) when it is turned off. This imbalance caused by circuit layout will cause some devices to have too much current during the switching process, while other devices have less current, resulting in current imbalance.

Therefore, to solve the problem of current imbalance during switching, it is necessary to comprehensively consider and optimize the device's electrical characteristics and layout . First, the gate-emitter Vgs(e)th of the power devices at the nominal operating current is carefully screened and sorted to ensure that the difference in Vgs(e)th of each device is controlled within 0.1V, which helps to achieve more consistent switching behavior. Secondly, in order to balance the current, it is necessary to ensure that the loop length between each power device and the gate-level driver is consistent, which helps to reduce the inconsistent switching time caused by loop differences. Finally, symmetrical stray inductance design is equally important. In the circuit layout, it is necessary to ensure that the stray inductance from the source or emitter of the power device to the driver IC is symmetrical and as equal as possible.

The gate oscillation problem originates from the differences in the connection between chips and external circuits when power devices are used in parallel. These conditions together may cause LC resonance . Specifically, each chip has parasitic input capacitance Cgd and Cgs. When there is stray inductance between the common gate and source between chips, LC resonance may occur between chips. In addition, slight differences in the parameters of the chip itself, such as different threshold voltages Vgs(th), and different stray inductances between the externally connected source and driver, may also contribute to this resonance. If there is not enough impedance in the circuit to dissipate this energy, resonance will occur, causing the gate voltage Vgs to oscillate.

This oscillation not only increases the switching loss of the power device, but may also cause repeated switching, which may cause the power device to be damaged due to excessive losses in the long run. Therefore, in order to reduce the risk of gate oscillation, it is necessary to consider matching the stray inductance between chips during design, and ensure that the stray inductance between the source (Source) and drain (Drain) of the parallel chips (such as LD1 and LD2, LS1 and LS2, LG1 and LG2 in the figure above) is equal or as close as possible to reduce LC resonance caused by inductance mismatch. If the internal gate resistance of the chip is zero ohm or very low, an external gate resistor (Rg) should be configured separately for each device. This helps to consume the energy generated by LC resonance and reduce gate oscillation.

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