Product Recommendations | SiC MOSFET packaging, system performance and applications

WBG semiconductors enable high-voltage converters to operate closer to the switching frequencies of low-voltage converters (sub-100V). For low-voltage converters, developments in semiconductor packaging have played a key role in achieving today's switching performance. There have been advancements in silicon MOSFET packaging such as double-sided cooling, clamp bonding, thermally enhanced power packaging and low-inductance, leadless packaging. Similarly, the gate driver IC package has also been significantly slimmed down. Shorter chip-to-lead, bond wire connections, coupled with molded leadless packaging (MLP), are critical to minimizing parasitic inductance on the driver side. Co-packaging of drivers and MOSFETs (DrMOS) is the latest step in reducing parasitic inductance, improving efficiency and shrinking board area. DrMOS was also made possible by the introduction of packaging improvements similar to those used in low-voltage converter applications.

In the field of high-voltage converters, minimum spacing requirements such as creepage distance and clearance require high-performance SiC MOSFETs to still use low-performance To-220 and To-247 packages. These packages are well established and have long been the industry standard. They are ideal for industrial applications, are robust and easily dissipate heat, but their long leads and internal bond wires result in higher parasitic inductance. SiC MOSFETs now enable these parasitic inductances to be affected by thermal stress, frequency and dV/dt rates, which was never previously envisaged in high-voltage silicon transistors. It can be said that SiC promotes the rethinking of high-voltage discrete packaging.

Unlike discrete devices, SiC gate drivers can take advantage of packaging improvements in driver devices originally intended for low-voltage power converters. The NCP5170 chip is packaged as a 24-pin, 4x4 mm, thermally enhanced MLP, as shown in Figure 15.

Figure 15. NCP51705 24-pin, 4x4mm, MLP package and pinout

All high current power supply pins are distributed in two, located on the right half of the IC. Additionally, these pins are all connected to the chip via internal double bond wires for the lowest possible inductance. All low-power digital signals are single-pin only and are located on the left half of the IC, providing a convenient, direct interface to a PWM or digital controller.

The bottom of the NCP51705 package includes an electrically insulating, thermally conductive, exposed pad. This pad is not connected to PGND or SGND but is connected to an isolated copper PCB pad via thermal vias for heat dissipation.

If cooling becomes an issue, there are four main power consumption factors that should be paid special attention to:

For V _DD >7V, the quiescent current ramps up linearly until it exceeds the set UVLO threshold. The blue curve shown in Figure 16 represents the variation curve of V _DD relative to I _{DD when there is no PWM input signal and V DD(UVLO)} =12V, and the V5V regulator has no load . For 7V<V _{D D} <22V, I _DD measures 0.6mA<I _DD <2.3mA. The flat line segment in the middle indicates that when V _exceeds the UVLO threshold, the I _current increases by approximately ~1mA.

The red curve represents a 100kHz, 50% duty cycle pulse input applied to IN+ while the internal charge pump is disabled. Use a 4.99Ω+2.2nF load, which is the equivalent input impedance of a typical SiC MOSFET. The external sink and pull resistor is 3Ω. For 12V<V _DD <22V, I _DD measures 3.7mA<I _DD <5.5mA.

Figure 16. V _DD vs. I _DD , non-switching vs. switching

The startup waveform shown in Figure 17 shows that the PWM signal has been input to IN+ before V _DD . V _DD rises from 0V to 20V, UVSET=2V (not shown in the figure), which is equivalent to V _DD(UVLO) =12V. V _EE is set to regulate at −5V, VEESET=V5V (not shown in the figure), which is equivalent to V _EE(UVLO) =−4V. When V _EE =−4V, the output is enabled, and V _DD >12V (V _DD =15V). Also note that OUT(V _GS ) is less than 20V for nearly 100µs . Depending on the dV/dt rate at which VDD _ramps up, this time may be longer, so thermal stress on the SiC MOSFET should be considered when programming UVSET.

Figure 17. CH1-IN+, CH2-V _DD , CH3-OUT, CH4-V _EE;

V _DD(UVLO) =12V, V _EE(UVLO) =-4V

The same startup waveform is shown in Figure 18, but with UVSET=3V (not shown), which is equivalent to V _DD(UVLO) =18V. In this case, OUT(V _GS ) is enabled when V _{DD =18V and V EE} <−4V (V _EE =−5V). Which UVLO dominates depends on the dV/dt rates of V _DD and V _EE . The key point is that the NCP51705 output is disabled until both V _DD and V _EE are above or below their respective UVLO thresholds. Note the effect of higher UVLO settings on OUT(V _GS ) compared to Figure 17, where the first OUT pulse occurs around 20V and −5V.

Figure 18. CH1-IN+, CH2- V _DD , CH3-OUT, CH4- V _EE ;

V _DD(UVLO) =18V, V _EE(UVLO) =-4V

The NCP51705 internal charge pump has a slow control loop, the effect of which can be seen in the slight undershoot and <400μs settling time observed during V _EE startup, as shown in Figure 19. Over 400µs, the V _EE voltage stabilizes to the regulated set value of −3V, −5V, or −8V.

Figure 19.V _EE startup

The shutdown operation is smooth and glitch-free. As shown in Figure 20, OUT stops switching and tracks V _EE upon power-down . The discharge time of V _EE from −5V to 0V is approximately 300ms.

Figure 20.CH1-IN+, CH2- V _DD , CH3-OUT, CH4- V _EE ; closed

Figure 21 shows an enlarged view of the time base in Figure 20. UVSET is configured to 3V (V _DD(UVLO) =18V), and the internal V _DD UVLO hysteresis is internally fixed to 1V. When the output is disabled, the cursor position shows V _DD =17V (18V−1V hysteresis), when V _EE =−4.5V (VEESET=V5V), and the −4V UVLO is still within the valid voltage range. Although V _DD decays slowly, after UVLO_OFF, you can also see a clean termination of the last output pulse with no spurious pulses or glitches.

Figure 21.CH1-IN+, CH2-V _DD , CH3-OUT, CH4-V _EE ;

Off, V _DD _UVLO(OFF)=17V

The measurement range for conduction propagation delay increases from 90% IN+ to 10% OUT. Typically SiC drivers will operate at higher V _DD , but most SiC MOSFET propagation delays are specified at V _DD =12V, measured at 1nF load condition. Figure 22 shows the measured turn-on propagation delay of 19ns under these standard test conditions.

Figure 22.CH1-IN+, CH2- V _DD , CH4-OUT; rising edge propagation delay

Likewise, the turn-off propagation delay is measured from 10% IN+ down to 90% OUT down. Figure 23 shows the measured turn-off propagation delay of 22ns under the same standard test conditions. The output rise and fall times for each edge are approximately 5ns.

Figure 23.CH1-IN+, CH2- V _DD , CH4-OUT; falling edge propagation delay

The DESAT and XEN waveforms are shown in Figure 24 and Figure 25 respectively. Since the test is for IC verification only (no power device level), connect the 100pF fixed capacitor to the DESAT pin. The waveform shown in Figure 24 shows that DESAT is below the 7.5V threshold and the output switches during normal operation. If the IN+ frequency decreases (on-time increases), the 100pF DESAT capacitor will be able to charge to a higher voltage. As shown in Figure 25, the DESAT voltage has reached the 7.5 threshold. The output trailing edge terminates before the input voltage switches low. The small DESAT ramp is used to emphasize the fact that no glitches occur on the terminated OUT pulse. In switching power supply applications, a small (<100pF) external capacitor can be used on the DESAT pin for high frequency noise filtering.

The XEN signal is the opposite of the OUT signal. Whether the drive is operating normally or facing a DESAT failure, the XEN signal accurately tracks the reverse OUT signal in either case.

Figure 24.CH1-IN+, CH2-OUT, CH3-DESAT, CH4-XEN; V _DESAT <7.5V

Figure 25.CH1-IN+, CH2-OUT, CH3-DESAT, CH4-XEN; V _DESAT =7.5V

SiC MOSFET can be applied to various application scenarios where IGBT is currently used. Some of the more common uses include high-voltage switching power supplies, hybrid and electric vehicle chargers, electrified rail transportation, welders, lasers, industrial equipment and other environments where high-temperature operations are critical. Two areas in particular that deserve mention are solar inverters and high-voltage data centers. Higher DC voltages help reduce wire gauge thickness, junction boxes, interconnections, and ultimately minimize conduction losses, thereby increasing efficiency. At present, most large-scale photovoltaic systems use 1kV DC bus, and they will tend to use 1.5kV bus in the future. Likewise, a data center using a 380V power distribution network can boost the DC voltage to 800V.

Several basic application examples of the NCP51705 are shown below.

Figure 26 shows the top-level schematic of the NCP51705 for low-side switching applications. Isolation is not shown, so there is a direct interface between the controller and the drive, and not all applications are non-isolated architectures. This schematic is intended to illustrate how few external components are required to provide a fully functional, reliable and robust SiC gate drive circuit. It should also be mentioned that although only a single V _DD voltage rail is required, its common mode transient immunity rating should be at least 50V/ns to prevent discrete gate drive in the discrete SiC gate drive section Describe the stray current pulse described. If the V _DD rail is supplied from a dedicated auxiliary supply, special attention should be paid to designing the transformer with ultra-low primary-to-secondary stray capacitance.

Figure 26. Low-side switch example

A more common use of SiC MOSFETs can be found in half-bridge power topologies, as shown in Figure 27. High power applications tend to use isolated drivers on both the high and low sides. This means two digital isolators are required. Depending on the number of IO interfaces crossing the isolation boundary, secondary-side control of such applications can be quite contentious. In this simplified example, In+ and In- (enable) are the only two signals from the digital controller, and XEN is read from the NCP51705. XEN can be used as a baseline for timing information for developing gate drive timing, cross-conduction prevention, dead time adjustment and fault detection. Additionally, temperature sensing, thermal management (fan control) and higher level fault response can also be accomplished by digital controllers. The V5V of the NCP51705 can be used to power the secondary side of each digital isolator, as shown in Figure 27.

Figure 27. Half-bridge concept

A 100W QR flyback converter was designed using the NCP1340B1 controller and NCP51705 SiC driver to operate over a wide input range of 300V < V _IN < 1kV. Such converters are commonly found in photovoltaic and industrial applications, but when based on IGBT power stages, the switching frequency is in the range of 65kHz. The schematic diagram shown in Figure 28 is a QR flyback. When V _IN =300V, the frequency changes between 377kHz<Fs<430kHz, and the load varies from 100% to 25%.

Figure 28.1000V to 24V, 100W, 400kHz, QR flyback

For V _IN =300V, the drain-source voltage waveform is the sum of the input voltage and the reflected output voltage. The waveforms shown in Figure 29 highlight the converter operating at full duty cycle operation (V _IN =300V), where the drain-source voltage of the SiC MOSFET is 720V. The V _DS rising transition is about 30ns, which is equivalent to dV _DS /dt=24V/ns. The NCP1340B1 QR control achieves soft resonant transition and valley switching on the falling edge of V _DS ( turning on "near ZVS" when V _DS resonates to a minimum). This operation process can be clearly seen on the blue waveform. Since QR flyback is a low-side switching application only and the dV _DS /dt falling edge is resonant, the SiC MOSFET may switch reliably between 0V < V _GS < 20V. Nonetheless, the design shown in Figure 28 chooses to switch between −5V < V _GS < 20V, resulting in more robust switching at the slight cost of increased gate charge.

Figure 29.CH3=V _DS , CH4=V _GS ; V _IN =300V, V _OUT =24V,

I _OUT =4A, F _S =377kHz

The universal evaluation board (EVB) is designed to evaluate the performance of the NCP51705 in new or existing designs. EVB does not include power stages and is not dedicated to any specific topology, making it universal. It can be used in any low-side or high-side power switching application. For a bridge configuration, two or more EVBs can be used to form a totem pole structure to drive each SiC MOSFET. EVB can be considered as isolator + driver + TO-247 discrete module. The EVB schematic diagram is shown in Figure 30.

The focus is to provide an ultra-compact design in which the leads of the TO-247 SiC MOSFET can be connected directly to the printed circuit board (PCB). Figure 31 shows both the top and bottom views of the EVB next to the adjacent TO-247 package scaled for size.

Figure 30.NCP51705 Mini EVB schematic

Figure 31.NCP51705 Mini EVB-top view (35mmx15mm)

When installing into an existing power supply design and there is available PCB area in front of the TO-247, the EVB can be mounted horizontally to the main power supply board as shown in Figure 32. If possible, this should be the preferred installation method.

Figure 32. Horizontal EVB installation

If large components on the main power board prevent horizontal mounting, a second option is to mount the EVB vertically, parallel to or slightly angled from the T0-247 package. Since the driver is very close to the high dV/dt emitted by the TO-247 drain connector, it is less likely to be mounted this way. In either case, the TO-247 package's rear header remains exposed and can be connected to a heat sink if necessary. See the EVB User Guide for installation and operational details.

Figure 33. Vertical EVB installation

The EVB is initially configured to accept a PWM signal of positive input logic (IN- connected to GND1). But if desired, IN- can easily be used as an active enable or reconfigured as inverting input logic. The driver outputs are preconfigured for 0V < V _OUT < V _DD switching. All connections and resistor placeholders can be used to reconfigure VEESET for −3V, −5V, or −8V VEE switches _. Finally, the UVSET option is preprogrammed for 17-V turn-on operation, which is considered the safe turn-on voltage for most SiC MOSFETs.

Parametric characterization of MOSFETs and IGBTs is performed using the well-known double-pulse test platform. The double-pulse test method basically applies two pulses to the gate-source of the low-side SiC MOSFET of the device under test (DUT). The DUT is plugged into a socket connected to the clamped inductor switching circuit shown in Figure 34.

Figure 34. Double pulse test circuit and waveforms

Adjust the on-time of the first pulse to obtain the desired peak drain-source current. The inductor is large and the off time is short enough so that IL1 _remains almost constant during off freewheeling. Therefore, a second, shorter pulse is applied with the same drain-source current amplitude. This test method provides precise control of I _D and V _DS , which is necessary to establish dynamic switching, parametric performance, and comparative testing of devices.

The double-pulse test method can also be used to characterize gate driver performance. When SiC and DUT are fixed, U1 can be composed of various gate drive circuits _to become a new "DUT". The dV/dt and dI/dt switching performance is compared between the NCP51705 EVB shown in Figures 30 and 31 and the simple optocoupler gate drive circuit shown in Figure 35.

Figure 35. FOD8384 SiC optocoupler gate drive circuit

The FOD8384 optocoupler driver is capable of tolerating V _DD bias voltages up to 30V, making it ideal for -5V < V _GS < 20V switching. Similar to the example in Figure 8, the FOD8384 driver is not a complete SiC MOSFET gate drive circuit. Therefore, since the characteristics of the two circuits are not comparable, the test results and comparisons are limited to dynamic switching.

Figure 36 and Figure 37 show the rising and falling V _GS waveforms for both circuits, respectively, for comparison. Both circuits use 1Ω sink and pull resistors. These gate drive edges are shown driving a 1.2kV SiC MOSFET with 600V on V and 30A flowing _through ID _. NCP51705, V _GS rising edge behaves as pure resistance when −5V<V _GS <10V, and then charges capacitive RC when 10V<V _GS <20V. This shows how the current sink of the NCP51705, 6 A _{PK compares to the 1 A PK} sink of the FOD8384. The V _GS rise time of the NCP51705 is 37.5ns, while the FOD8384 switch is 57.6ns under the same test conditions. Likewise, the NCP51705’s V _GS fall time is 25.2ns, while the FOD8384’s is 34.5ns.

Figure 36. V _GS rising edge comparison

Figure 37. V _GS falling edge comparison

A well-designed gate driver IC includes low source and drain resistance so that the SiC MOSFET drain can be precisely controlled by the gate. Second, minimizing driver output impedance is critical to allowing SiC MOSFETs to reach their highest natural dV/dt. The natural dV/dt limit of a SiC MOSFET is inversely proportional to R _LO + R _GATE + R _GI . When R _LO is higher than necessary, the SiC MOSFET's natural dV/dt limit is reduced. This makes the device more susceptible to dV/dt induced turn-on and limits the amount of dV _DS /dt control that can be achieved by selecting R _{GATE . The NCP51705 V DS} waveform shown in Figure 38 reveals the high degree of dV _DS /dt control that can be achieved by changing R _GATE . For R _GATE =1Ω, dV _DS /dt=72V/ns. Increasing R _GATE from 1Ω to 15Ω reduces dV _DS /dt from 72V/ns to 68V/ns. This shows that a much higher R _GATE can be used to gradually reduce dV _DS /dt if desired.

Figure 38. NCP51705 V _DS rising edge, variable gate resistance

The same experiment was done using the FOD8384 optocoupler gate driver. From the waveform shown in Figure 39, it is found that changing R _GATE from 1Ω to 15Ω causes the dV _DS /dt rate to change by more than 2:1. Due to the higher output impedance of the FOD8384 driver, the dV _DS /dt control is more affected by smaller changes in R _GATE . Also note that the dV _DS /dt rise of the NCP51705 is relatively more linear.

Figure 39. FOD8384 V _DS rising edge, variable gate resistance

The waveforms shown in Figure 40 compare V DS for each driver switching the same load from −5V < V _{GS <20V with R GATE} =1Ω _. The dV _DS /dt rates are equivalent at 72V/ns and 64V/ns. Exhibits faster ring decay and lower ring amplitude.

Figure 40. V _DS rising edge comparison, 1Ω gate resistance

Another way the NCP51705 achieves dV _DS /dt control is by changing the negative amplitude level of V _EE . This can be accomplished by configuring the VEESET pin according to Table 3 or by using an external negative DC supply applied to V _EE . The waveform in Figure 41 shows the change in dV _DS /dt as V _EE varies between −6V < V _EE <0V . Note the strong knee point and capacitive behavior at low V _{DS at 0V<V GS} <20 V. This is because the SiC MOSFET has some residual gate charge that does not turn off completely and highlights the importance of driving the V negative terminal _{during turn-off.}

Figure 41.NCP51705 V _DS rising edge, variable V _EE

The drain current measurement shown in Figure 42 was made using a Pearson current probe. The NCP51705 current drops at dID _/dt=3.2A/ns , but exhibits less ringing than the FOD8384 driver circuit. The faster dID /dt of the NCP51705 _{correlates well with the V GS} falling edge waveform shown in Figure 37 .

Figure 42. _ID falling edge comparison

The double-pulse test method is a test procedure traditionally used to characterize the dynamic switching performance of discrete power semiconductor devices. Because the applied V _DS and initial ID _can be precisely controlled during turn-on and turn-off , this measurement technique has proven to be a reliable method for characterizing the performance of gate driver ICs in clamped inductive switching application circuits.

This article highlights some of the characteristics of SiC MOSFETs that must be considered when designing high-performance gate drive circuits. For gate driving, the low gm or not-so-large transconductance characteristics associated with SiC MOSFETs is particularly tricky. Generic low-side gate drivers are often used but lack the necessary features to drive SiC MOSFETs efficiently and reliably. The widespread adoption of SiC MOSFETs in the market is partly related to their ease of use. The NCP51705 provides designers with a simple, high-performance, high-speed solution for driving SiC MOSFETs efficiently and reliably.

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