Further improving the efficiency of 48V to 12V power supply solutions

48 V配电轨通常会降压至某个中间电压，往往是12 V或更低，然后不同的本地负载点稳压器直接向不同负载提供各种不同的电压。对于48 V至12 V降压调节器，首选之一是多相降压转换器（图1）。这种解决方案提供稳压VO和快速瞬态性能，很容易实现且成本较低。对于几百瓦到>1 kW的功率范围，可以考虑四相并联。然而，高效率通常是一个优先考虑因素，与12 V甚至5 V输入的较低电压应用相比，48 V转换器为了保持低开关损耗，开关频率通常相对较低。这会在"伏特×秒"方面对磁元件造成双重损害，因为已经很明显的电压也会作用相对较长的时间。因此，与较低电压应用相比，48 V的磁元件通常体积较大，并使用多匝绕组来承受显著提高的"伏特×秒"。48 V降压转换器仍然可以实现高效率，但整体尺寸通常相当大，其中电感占据了大部分体积。

基本48 V至12 V ~1 kW降压转换器具有四相，使用6.8 μH分立电感，开关频率为200kHz。这四个电感是目前最大和最高的元件，占解决方案体积的大部分。本文的目标是保持或提高此初始设计所实现的高效率，但显著减小磁元件的尺寸。

The current ripple of each phase of a conventional buck converter can be calculated by Equation 1, where the duty cycle is D = V _O /V _IN , V _O is the output voltage, V _IN is the input voltage, L is the inductance value, and F _s is On-off level.

Replacing the discrete inductor (DL) with a coupled inductor with leakage inductance L _k and mutual inductance L _m , the current ripple in CL (coupled inductor) can be expressed as Equation 2. FOM is expressed as Formula 3, where N _ph is the coupling phase number, ρ is the coupling coefficient (Formula 4), j is the operating index, and only the applicable interval of the duty cycle is defined (Formula 5).

The first step in improvement is to draw the FOM curve of N _ph = 4 for several practical and reasonable values ​​of the coupling coefficient L _m /L _k (Fig. 2). The red curve L _m /L _k = 0 represents the FOM = 1 baseline of the discrete inductor. It has been demonstrated that notch CL (NCL) structures with very low leakage inductance generally achieve very high L _m /L _k and therefore high FOM values. However, while ideally the target duty cycle is exactly at the first notch D = 12 V/48 V = 0.25, it is necessary to consider a certain range of V _IN and _VO . Sometimes the nominal V _IN can be 48 V or 54 V plus some tolerance, VO _can be adjusted away from 12 V, etc. If the duty cycle varies within a certain range around D = 0.25, in order for the current ripple to be always suppressed, a typical CL design with considerable leakage inductance should be chosen instead of NCL, but the FOM value is still quite large. Assuming L _m /L _k > 4, reducing the inductance value in CL may improve the FOM in Figure 2 by a factor of approximately 6 compared to the DL baseline. Reducing energy storage has a direct impact on the required magnetic component volume. Therefore, reducing DL = 6.8 μH to CL = 1.1 μH should facilitate size reduction.

Figure 3 shows the corresponding current ripple, comparing the baseline design DL = 6.8 μH with the recommended 4-phase CL = 4 × 1.1 μH (Lm = 4.9 μH) at V _IN = 48 V and F _s = 200 kHz. . In the target area, the current ripple of CL is similar to or smaller than that of DL. This means that all circuit waveforms have similar rms and conduction losses are similar. The same ripple at the same Fs also means that the switching losses, gate drive losses, etc. are also the same, so the efficiency of the two solutions should be very similar (assuming similar contributions from the DL and CL inductor losses, which is the only difference).

Figure 4 shows the design with CL = 4 × 1.1 μH, which replaces the four DL = 6.8 μH inductors. 5 The size of each DL is 28 mm × 28 mm × 16 mm. Assuming that they are spaced 0.5 mm from each other, a 4-phase CL with a size of 56.5 mm × 18 mm × 12.6 mm can reduce the volume of the magnetic component to 1/ 4. Figure 5 shows the complete 1.2 kW 48 V to 12 V regulation solution with the components on one side of the PCB located within the 1/4 brick outline. The CL size and package are designed so that two CL elements can fit within the industry standard quarter-brick footprint. Placing all ~1 mm components (FETs, controller ICs, ceramic capacitors, etc.) on the bottom of the PCB results in a 1.2 kW solution in 1/8 brick size.

When the DL = 6.8 μH inductor changes to CL = 4 × 1.1 μH, the current slew rate limit in the inductor is also improved by a factor of 6, which helps improve transient performance. In addition to this, the inductor saturation rating at 100°C is increased by approximately a factor of 2, although the total magnetic component volume is reduced to 1/4 of the original size.

Figure 6 shows the transient performance of the proposed V _IN = 48 V solution (output V _O = 12 V). As expected, for varying load currents, feedback regulates the output voltage to a preset value while compensating for any changes in input voltage.

The efficiency achieved is shown in Figure 7 and is probably the overriding performance parameter. It is compared with an advanced industry solution: 48 V to 12 V (fixed 4:1 step-down) LLC with matrix transformer and GaN FETs on both primary and secondary sides. 10 The achieved full load efficiency is 97.6%, compared to the baseline efficiency of 96.3%. This represents a 16.6 W reduction in losses at full power, and the proposed solution achieves a 1.6x improvement. When efficiency is already so high, reducing losses by such a large margin is often difficult to achieve.

Tradeoffs between size and efficiency are certainly possible. Figure 8 compares the efficiency of CL = 4 × 1.1 μH (magnetic element size reduced to 1/4 of DL) and the larger CL = 4 × 3 μH (inductor volume reduced to only 1/2 of DL). The physically larger CL = 4 × 3 μH has a higher leakage inductance L _k = 3 μH and a larger mutual inductance L _m = 10 μH. This allows Fs to be easily reduced to 110 kHz, thereby significantly improving efficiency over the entire load range.

Taking advantage of coupled inductors, the 48 V to 12 V solution reduces the total magnetic component size to 1/4 that of a basic discrete inductor, achieving 1.2 kW in an industry standard 1/8 brick size. It maintains excellent efficiency performance while reducing magnetic component size by 4x, with a 6x increase in transient inductor current slew rate and a 2x increase in inductor I _{sat rating.}

It reduces losses by approximately 1.6x at full power compared to industry-leading 48 V to 12 V solutions of the same size. Efficiency could be further improved if the size of the magnetic components could be reduced less drastically.

At the same time, the proposed solution provides excellent regulated output, can be placed directly on the customer's motherboard, and utilizes standard silicon FETs to further optimize costs. In contrast, the unregulated 4:1 LLC with all-GaN FETs is manufactured as a separate module and uses a dedicated PCB with multiple layers, sensitive layout and embedded matrix transformers.

The overall performance improvements demonstrate the benefits of ADI’s patented IP for coupled inductors, which we are pleased to make available to numerous customers for dc-to-dc applications.