Revealed! What benefits does RF sampling ADC bring to system design?
Data converters have been bridging the gap between the analog and digital worlds for decades. From discrete components that took up multiple rack spaces and consumed a lot of power (e.g., 500W for a DATRAC 11-bit 50kSPS vacuum tube ADC), data converters have evolved into highly integrated single-chip ICs. Ever since the first commercial data converters were introduced, the insatiable demand for faster data rates has driven data converters forward. The new incarnation of the ADC is the RF sampling ADC with sampling rates into the GHz range.
Early ADC designs used very little digital circuitry, primarily for error correction and digital drivers. The new generation of GSPS (gigasamples per second) converters (also known as RF sampling ADCs) is implemented using cutting-edge 65 nm CMOS technology, which can integrate many digital processing functions to enhance ADC performance. In this way, data converters have evolved from the large A (analog) small D (digital) ADCs of the mid-1990s and early 2000s to the small A large D ADCs of today.
This does not mean that analog circuitry and its performance has declined, but rather that the amount of digital circuitry has increased significantly to complement the analog performance. These added features allow the ADC to quickly perform a lot of digital processing in the ADC silicon, offloading some of the digital processing load from the FPGA. This opens up many other possibilities for system designers. Now, with these advanced new GSPS ADCs, system designers only need to design one hardware for a wide variety of platforms, and then efficiently reconfigure the hardware in software to adapt to new applications.
The combination of shrinking CMOS process geometries and advanced design architectures meant that ADCs could finally take advantage of digital processing techniques to improve performance. The breakthrough was made in the early 1990s, and ADC designers have never looked back since then. As silicon processes have improved (from 0.5 μm, 0.35 μm, 0.18 μm to 65 nm), conversion speeds have also increased. However, shrinking geometries have made transistors smaller, and while faster (and therefore higher bandwidth), some characteristics have become slightly worse in terms of analog design performance, such as Gm (transconductance). Previously, this was compensated by adding more correction logic. However, silicon was still expensive at the time, resulting in a relatively small amount of digital circuitry inside the ADC. Figure 1 shows a functional block diagram of an example.
Figure 1. Early single-chip ADCs with minimal digital error correction logic.
As silicon technology advances to deep submicron dimensions (e.g., 65 nm), in addition to the ability to run faster cores (1 GSPS or more), economies of scale allow data converters to add a lot of digital processing. This is a breakthrough after re-examination. Typically, digital signal processing is handled by either ASICs or FPGAs, depending on system performance and cost requirements. ASICs are dedicated circuits that cost a lot of money to develop. Therefore, designers often keep ASIC designs running for a long time to extend the return on investment in ASIC development. FPGAs are cheaper than ASICs and do not require a huge development budget. However, as FPGAs seek to support all applications, their signal processing capabilities are limited by speed and power efficiency. This is understandable because it has flexibility and reconfiguration capabilities that ASICs do not have. Figure 2 shows a functional block diagram of an RF sampling ADC (also known as a GSPS ADC) with configurable digital processing blocks.
Figure 2. GSPS ADC with integrated digital processing blocks.
The new generation of GSPS ADCs will revolutionize radio design because they provide tremendous design flexibility, some of which are discussed below.
Early radios used a hybrid of analog mixers and cascaded digital downconverters (DDCs) to downconvert signals to baseband for processing, which involved a lot of hardware (analog mixing) and power (both in the analog domain and in the DDC domain in the ASIC/FPGA). The advent of a new generation of RF sampling ADCs has enabled the DDCs to run at high speeds inside the ADC filled with custom digital logic, which means much more power efficient processing.
The new generation of RF sampling ADCs not only has GSPS sampling capability, but also abandons the outdated LVDS output and adopts a high-speed serial interface. The new JEDEC JESD204B specification allows digital output data to be transmitted at a high channel rate of up to 12.5 Gbps per channel through CML (current mode logic), which provides a high level of I/O flexibility. For example, the ADC can operate in full bandwidth mode and transmit digital data on multiple channels, or use one of the available DDCs and transmit extracted/processed data on one channel, as long as the output channel rate is less than 12.5 Gbps per channel.
The use of DDCs provides greater flexibility in hardware design. System designers can now freeze the hardware design of the ADC and FPGA, and then reconfigure the system to accommodate different bandwidths, as long as the ADC can support it, with only minor changes. For example, a radio can be designed as either a full bandwidth ADC (RF sampling ADC) or an IF sampling ADC (Intermediate Frequency ADC) using the provided DDCs. The only system changes will be on the RF side, with perhaps minimal additional mixing required for the IF ADC. The majority of changes will be in software, configuring the ADC to support the new bandwidth. However, the ADC + FPGA hardware design can remain largely unchanged. This results in a baseline hardware design that can be applied to many platforms, with software requirements being the only variable.
The high level of integration brought by deep submicron CMOS processes has ushered in a new era of ADCs - more and more features are built into the ADC. These include fast detection CMOS outputs that support efficient AGC (automatic gain control), as well as signal monitoring (such as peak detectors). All of these features help system design, reduce external components, and shorten design time.
A very common use case for ADCs is in communications receiver system design. Figure 3 shows the functional block diagram of an early generation radio receiver.
Figure 3. Wideband digital receiver for cellular radio.
The general specification of a GSM radio receiver requires the ADC to have a noise spectral density (NSD) of at least 153 dBFS/Hz or better. It is well known that the NSD has the following relationship with the SNR of the ADC:
NSD = SNR + 10 log10 (fs ÷ 2)
Where: The unit of SNR is dBFS
fs = ADC sampling rate
In wideband radio applications, it is not uncommon to sample and convert frequency bands up to 50 MHz simultaneously. In order to properly digitize a 50 MHz band, the ADC will need a sampling bandwidth of at least 5 times, or at least about 250 MHz. Substituting these values into the above equation, the SNR required for the ADC to achieve the –153 dBFS/Hz NSD requirement is about 72 dBFS.
Figure 4 shows the frequency plan used to effectively sample a 50 MHz band using a 250 MSPS ADC. The figure also shows the location of the second and third harmonic bands.
Figure 4. Frequency plan for a 50 MHz wideband radio using a 250 MSPS ADC.
The frequencies sampled by the ADC all fall within the first Nyquist (DC – 125 MHz) band of the ADC. This phenomenon is called aliasing, so these frequencies include the band of interest, the second and third harmonics that fold back or alias into the first Nyquist band, as shown in Figure 5, and explained as follows:
Figure 5. Usable frequency band shown in the first Nyquist zone, including second and third harmonics.
In addition to the NSD specification, cellular communication standards such as GSM, LTE, and LTE-A have other stringent requirements for SFDR (spurious-free dynamic range). This puts a lot of pressure on the front-end design; when sampling the signal in the frequency band of interest, the front end should be able to attenuate the interfering signal.
Note that the SFDR specification, i.e. the antialiasing filter requirement, is difficult to achieve for conventional radio front-end designs. The best antialiasing filter (AAF) solution to meet the SFDR requirement is to use a bandpass filter. Typically, such bandpass filters are fifth order or higher. A suitable ADC that can meet the SNR (or NSD) and SFDR requirements for such applications is the AD9467 16-bit 250 MSPS analog-to-digital converter. The front-end design for cellular radio applications using the AD9467 will look like Figure 6.
Figure 6. Front-end design including amplifier, antialiasing filter, and 250 MSPS ADC.
The frequency response of an AAF that meets the SFDR requirement is shown in Figure 7. This system is not impossible to implement, but there are many design challenges. The bandpass filter involves a large number of components and is one of the most difficult filters to implement. Component selection is very important and any mismatch will cause unwanted spurs (SFDR) in the ADC output. In addition to being very complex, any impedance mismatch will affect the gain flatness of the filter. In order to optimize this filter design to meet the passband flatness and stopband rejection requirements, considerable design work is required.
Figure 7. Bandpass response of the front end shown in Figure 6.
While the front-end implementation of this radio design is complex, it works, as shown by the SNR/SFDR performance vs. frequency plot in Figure 8.
Figure 8. SNR/SFDR vs. frequency for the 16-bit, 250 MSPS ADC design shown in Figure 6.
The FFT at 205 MHz is shown in Figure 9. However, the system implementation is complicated by the following reasons:
1. Filter design.
2. FPGA must provide dedicated I/O ports to capture LVDS data (16 pairs), which complicates PCB design.
3. The FPGA also needs to reserve some processing power for digital signal processing.
Figure 9. FFT of the 16-bit, 250 MSPS ADC design shown in Figure 6 at 205 MHz.
The RF sampling ADC approach uses oversampling techniques and then decimates the data to improve dynamic range. The speed advantages provided by deep submicron CMOS technology combined with high digital integration capabilities have ushered in a new era of RF sampling ADCs, which can now perform a lot of important processing rather than just simple analog-to-digital conversion. These ADCs have more digital circuits to support high-speed signal processing.
For the system designer, this means simplicity of implementation and additional flexibility that has traditionally been the domain of ASIC/FPGAs. The radio design example above can also be implemented using an RF sampling ADC. The AD9680 (14-bit, 1GSPS JESD204B, dual-channel ADC) is a new RF sampling ADC that also has additional digital processing capabilities. The NSD of this ADC at full rate (1 GSPS) is about 67dBFS. Don’t worry about the SNR yet, as you will find out later. The target frequency band is the same as before, but the frequency planning with respect to the Nyquist zone of the RF sampling ADC is much simpler, as shown in Figure 10. This is because the sampling frequency of this ADC (1 GHz) is four times that of the above example (250 MHz).
Figure 10. Frequency plan for a 50 MHz wideband radio using a 1 GSPS ADC.
From the frequency plan, it can be seen that the implementation is much simpler than that shown in Figure 4. The AAF requirements are also relaxed as shown in Figure 11. The idea of this approach is to use a simple analog front-end design and leave the digital processing blocks within the RF sampling ADC to perform the heavy signal processing.
Figure 11. AAF migration for 1 GSPS ADC
The benefit of oversampling is that the frequency plan is extended to the entire Nyquist zone, which is 4 times larger than the 250 MSPS Nyquist zone. This greatly reduces the filtering requirements and a simple third-order low-pass filter is sufficient instead of the band-pass filter used in the 250 MSPS ADC solution. A simplified AAF implementation using an RF sampling ADC is shown in Figure 12.
Figure 12. Front-end design including amplifier, antialiasing filter, and 1 GSPS ADC
Figure 13 shows the low-pass filter response. A band-pass filter is also shown for comparison. The low-pass filter has better passband flatness and is more manageable in terms of component mismatch. Impedance matching is also easier to achieve. In addition, the system cost is lower due to the reduced component count. The simplified front-end design reduces design time.
Because modern RF sampling ADCs integrate so much digital processing, digital processing can be performed at high speed inside the ADC. As mentioned above, this allows for power-efficient and I/O-efficient designs. System designers can now leverage their FPGA’s unused JESD204B transceivers to service data from other RF sampling ADCs that have already processed the data (analog-to-digital conversion, filtering, and decimation). This allows for efficient use of FPGA resources while increasing the channel count of the radio design.
Figure 13. AAF comparison of 250 MSPS ADC and 1 GSPS ADC
Using the DDC, the ADC can be used as a digital mixer to tune to any IF required by the design. This example also uses the frequency plan described above. The ADC performance is demonstrated using the ¼ decimation option and real mixing, as shown in Figure 14.
Figure 14. RF sampling rate is 1 GSPS, and DDC is set to decimate by 1/4.
In normal or full bandwidth mode, the AD9680 has an SNR of approximately 66 dBFS to 67 dBFS. When the DDC is active and the decimation ratio is ¼, an additional 6 dB of processing gain can be achieved [3]. This ensures that the dynamic range performance remains unchanged. Since the RF sampling ADC samples at 4 times the original sampling rate, the harmonics are spread (as shown in Figure 10). The DDC in the RF sampling ADC ensures that the decimation filter digitally attenuates the interfering signal. However, harmonics (higher order or otherwise) that fall within the band of interest will still show up because the DDC allows them to pass. This can be caused by amplifier artifacts or insufficient attenuation of the low-pass filter. The low-pass filter can be redesigned based on the system requirements to meet other spurious performance requirements.
Figure 15 shows the SNR/SFDR vs. input frequency for a 1GSPS ADC. The data clearly shows that the use of DDCs results in a 6 dB improvement in SNR (due to processing gain) and an improvement in SFDR. When operating in full bandwidth mode, the SFDR is typically limited by the second or third harmonic, whereas in DDC mode (¼ decimation), the limiting factor is the worst other harmonic.
Figure 15. SNR/SFDR vs. frequency for the 14-bit, 1 GSPS ADC design shown in Figure 12.
The FFT of the decimated output is shown in Figure 16. When using DDCs, steps must be taken to ensure that the frequency band of interest is properly processed. In this example, the NCO is tuned to 200 MHz so that the frequency band of interest is centered in the decimation Nyquist zone. The DDCs can easily remove unwanted frequencies from the spectrum. As a result, the FPGA has less processing overhead.
Figure 16. 205 MHz FFT of a 1 GSPS ADC with decimation by 4; NCO tuned to 200 MHz
For comparison, Figure 17 shows the FFT of the AD9680 in normal (full bandwidth) operating mode.
Figure 17. 205 MHz FFT of 1 GSPS ADC in full bandwidth mode
From these graphs, we can see that in addition to improving in-band noise performance, the DDC also provides a clean spectrum without interfering harmonics. As the DDC filters and decimates the data (to 250 MSPS), it also reduces the output lane rate, which makes the JESD204B serial interface have more flexible options. System designers can choose a high lane rate (more expensive), low I/O count FPGA or a low lane rate (less expensive), high I/O count FPGA.
RF sampling ADCs offer unique advantages to system design that were not available just a few years ago. The industry is looking to accelerate the design and implementation of infrastructure to handle higher bandwidth demands. Design times and budgets are shrinking, and the need for scalable, reconfigurable, and more software-driven architectures is driving new design paradigms. The need for higher bandwidth is accompanied by a need for higher capacity. This puts more pressure on FPGA I/Os, which RF sampling ADCs can address with internal DDCs.
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