Come and design an excellent power management solution for your FPGA application~

Finding the best solution for powering an FPGA is not simple. Many vendors market certain products as suitable for powering FPGAs. What are the specific requirements for selecting a DC-DC converter to power an FPGA? Not much. Generally speaking, all power converters can be used to power an FPGA. Recommendations for certain products are usually based on the fact that many FPGA applications require multiple voltage rails, such as for the FPGA core and I/O, and may also require additional voltage rails for DDR memory. Power management ICs (PMICs) that combine multiple DC-DC converters all into a single regulator chip are often the first choice.

A popular way to find a good power solution for a particular FPGA is to use an existing power management reference design that is available from many FPGA vendors. This is a good way to get started with an optimized design, but such designs often need to be modified because FPGA systems often require additional voltage rails and loads that also need to be powered, and it is often necessary to add something to the reference design. Another thing to consider is that the input supply to the FPGA is not fixed, and the input voltage depends a lot on the actual logic levels and the design implemented in the FPGA. After the modifications to the power management reference design are completed, it will look different from the original reference design. Some people may claim that the best solution is to not use a power management reference design at all, but to directly enter the required voltage rails and currents into a power management selection and optimization tool, such as LTpowerCAD from ADI.

Figure 1. Selecting a suitable DC-DC converter to power the FPGA using the LTpowerCAD tool.

LTpowerCAD can be used to provide power solutions for each voltage rail, and a series of reference designs are provided to get designers started quickly, and the tool can be downloaded for free. Once the power architecture and various voltage converters are selected, the appropriate passive components need to be selected to design the power supply. When doing this, it is necessary to keep in mind the special load requirements of FPGAs , which are:

The actual current consumption of an FPGA depends greatly on the use case. Different frequencies and different FPGA contents require different power, so the final power specifications of a typical FPGA design will inevitably change during the design process of the FPGA system. Power estimation tools provided by FPGA manufacturers can help calculate the power level required for the solution, and it is very useful to have this information before building the actual hardware. However, in order to obtain meaningful results with such power estimation tools, the design of the FPGA must be finalized, or at least nearly finalized.

Typically, engineers design the power supply with the maximum FPGA current in mind, and if it turns out that the actual FPGA design requires less power, the designer will scale back the power supply.

Many FPGAs require different power supply voltage rails to be powered up in a specific order. The core voltage often needs to be supplied earlier than the I/O voltage, otherwise some FPGAs will be damaged. To avoid this, the power supplies need to be powered up in the correct order. Simple power-up timing control can be easily implemented using the enable pins on standard DC-DC converters. However, component shutdown usually also requires timing control, and it is difficult to achieve good results by only performing enable pin timing control. A better solution is to use a PMIC with advanced integrated timing control functions, such as the power supply solution with integrated four-channel low-noise buck regulator - ADP5014 . The special circuit blocks shown in red in Figure 2 support the adjustment of power-up and shutdown timing.

Figure 2 PMICs incorporate support for flexible control of power-up/power-down sequencing.

Figure 3 shows the timing control implemented using this component. The time delay of the power-up and power-down timing can be easily adjusted through the delay (DL) pin on the PMIC.

Figure 3. Startup and shutdown sequencing of multiple FPGA supply voltages.

If multiple separate power supplies are used, adding a sequencing chip can achieve the required power-up/power-down sequence. An example is the LTC2924 quad power sequencer, which can control the enable pins of DC-DC converters to turn the power supplies on and off, and can also drive high-side N-channel MOSFETs to connect and disconnect the FPGA to a voltage rail.

In addition to voltage sequencing, the startup process may also require the voltage to rise monotonically, which means that the voltage only rises linearly, as shown by voltage A in Figure 4. Voltage B in this figure is an example of a non-monotonically rising voltage. This happens during startup when the load begins to draw large currents as the voltage rises to a certain level. One way to prevent this is to extend the soft-start time of the power supply and select a power converter that can quickly deliver large amounts of current.

Figure 4 Voltage A increases monotonically, while voltage B increases non-monotonically.

Another characteristic of an FPGA is that it will start drawing a lot of current very quickly, which can cause high load transients on the power supply. For this reason, many FPGAs require a lot of input voltage decoupling, and ceramic capacitors are used very closely between the VCORE and GND pins of the device, with values ​​of up to 1mF being very common. Such high capacitance helps reduce the need for the power supply to provide very high peak currents, however, many switching regulators and LDOs specify a maximum output capacitance, and the FPGA's input capacitance requirements may exceed the maximum output capacitance allowed by the power supply.

Power supplies do not like very large output capacitors because during startup, the output capacitors of the switching regulator appear to be a short circuit. There is a solution to this problem, a longer soft-start time allows the voltage on the large capacitor bank to rise steadily without the power supply going into short-circuit current limiting mode.

Figure 5 Input capacitance requirements for many FPGAs.

Another reason some power converters do not like excessive output capacitance is that the capacitance value becomes part of the regulation loop. Converters with integrated loop compensation do not allow excessive output capacitance to prevent the regulator loop from becoming unstable. Using a feedforward capacitor across a high-order feedback resistor can often affect the control loop, as shown in Figure 6.

Figure 6 When no loop compensation pin is available, the control loop can be adjusted using a feedforward capacitor.

For the load transient and startup behavior of the power supply, the development tool chain (including LTpowerCAD and especially LTspice) is very helpful. This tool can achieve good modeling and simulation, so as to effectively realize the decoupling of the large input capacitance of the FPGA and the output capacitance of the power supply. Figure 6 shows this concept.

While the point-of-load (POL) power supply is often located close to the load, there is often some PCB routing between the power supply and the FPGA input capacitors. When there are multiple FPGA input capacitors next to each other on the board, those farthest from the power supply have less impact on the power supply transfer function because there is not only some resistance between them, but also parasitic routing inductance. These parasitic inductances allow the FPGA's input capacitance to be larger than the maximum limit of the power supply output capacitance, even if all capacitors are connected to the same node on the board. In LTspice, parasitic routing inductances can be added to the schematic, and these effects can be simulated, and the simulation results are close to the actual results when enough parasitic components are included in the circuit modeling.

The voltage accuracy requirements for FPGA power supplies are usually very high, and a 3% variation tolerance band is quite common. For example, to keep the 0.85V Stratix V core voltage rail within the 3% voltage accuracy window, the total tolerance band is only 25.5mV, and this small window includes the voltage variation after load transients, as well as DC accuracy. Again, for such stringent requirements, the available power tool chain, including LTpowerCAD and LTspice, is very important in the power design process.

Figure 7 Parasitic decoupling between power supply output capacitance and FPGA input capacitance.

To quickly deliver large currents, ceramic capacitors are often chosen. These capacitors are well suited for this purpose, but care must be taken to select them so that their true capacitance does not drop with the DC bias voltage. Some ceramic capacitors, especially the Y5U type, can drop to only 20% of their nominal value when the DC bias voltage approaches their maximum rated DC voltage.

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