Example Deep Dive: Interleaved Inverting Charge Pump

As mentioned previously, IICP is used in integrated circuits to generate a small negative bias rail. The ADP5600 uniquely combines low noise IICP with other low noise features and advanced fault protection features.

The ADP5600 is an interleaved charge pump inverter with an integrated low dropout (LDO) linear regulator. Its unique charge pump stage provides lower output voltage ripple and reflected input current noise than traditional inductor or capacitor based solutions. Interleaving is a clever concept as a low noise concept, but interleaving channels does not solve all noise problems. To achieve true low noise, a specially designed IC is needed to realize the low noise benefits of IICP while keeping the solution small and efficient.

Many inverting charge pumps operate at frequencies of several hundred kHz. This relatively low frequency limit requires relatively large capacitors and limits where frequency spurs can be placed. The ADP5600 can operate at switching frequencies from 100 kHz to 1.1 MHz, allowing it to be used efficiently in modern systems. In addition, the frequency is always fixed and does not vary with output load. Switching frequency variation (spread spectrum modulation) is often used to improve charge pump efficiency, but can be problematic in noise-sensitive systems.

Many low noise systems require that high amplitude switching noise be placed within a specified frequency band so that the resulting noise has minimal impact on the system. With this in mind, in noise sensitive systems the operating frequency of the converter is synchronized, but synchronization is rare in charge pump inverters. In contrast, the ADP5600 can be synchronized to an external clock up to 2.2 MHz.

The input voltage range of the ADP5600 is wide, and its charge pump output voltage may be too high to power low voltage circuits. Therefore, the ADP5600 has an LDO post regulator built in. It also has a positive voltage referenced power good signal pin to allow easy power sequencing when the LDO output is in regulation.

Finally, the ADP5600 has a comprehensive set of fault protection features for robust applications. Protection features include overload protection, short-circuit flying capacitor protection, undervoltage lockout (UVLO), precision enable, and thermal shutdown. Another novel feature is the flying capacitor current limit, which also reduces the peak current spike when the flying capacitor is charged.

之前我们从理论上证明了与非交错解决方案相比，IICP架构可显著改善纹波。为简洁起见，但是其中说明的推导是理想化的，忽略了寄生效应、布局依赖性（IC和PCB）、时序失配（即不完美的50%振荡器）和R _DS 失配。这些因素导致与计算和测量的电压纹波有些偏差。一如既往，最好将ADP5600投入使用，观测其性能，并使用推导的方程式指导电路优化以获得最佳性能。

_{Here, the standard ADP5600 evaluation board is used, but R FLY} is inserted and the values ​​of C _FLY and C _OUT are modified . In addition, the SYNC feature of the ADP5600 is used to change the switching frequency. The block diagram in Figure 1 shows that each charge pump switches at half the SYNC frequency. In other words, f _OSC = ½ f _SYNC .

Figures 3 and 4 show the output voltage ripple of an interleaved and non-interleaved inverting charge pump, respectively, operating under the same conditions.

Figure 1. Simplified block diagram of the ADP5600 interleaved inverting charge pump.

Figure 2. ADP5600 interleaved inverting charge pump test setup.

Figure 3. ADP5600 IICP output voltage, V _IN = 6 V, C _OUT = C _FLY = 2.2 μF, f _OSC = 250 kHz, I _LOAD = 50 mA

Figure 4. Standard inverting charge pump output circuit, V _IN = 6 V, C _OUT = C _FLY = 2.2 μF, f _OSC = 250 kHz, I _LOAD = 50 mA

Under these conditions, the input and output voltage ripple of the ADP5600 is almost 14 times lower than that of a conventional inverting charge pump. The output (or input) voltage ripple of the IICP is given by:

Using Equation 1 and substituting actual values ​​for R _OUT and R _ON , the calculated and measured output voltage ripple can be compared. Table 1 shows the results for a variety of test configurations and indicates the improvement over the non-interleaved charge pump solution.

_{Table 1. V OUT} ripple for different use cases ; V _IN = 12 V, I _LOAD = 50 mA, R _ON = 2.35 Ω*

_{* Actual capacitance values ​​of C OUT} and C _FLY are used (capacitors are derated at voltage), not nominal values.

Table 1 shows that the interleaved voltage ripple agrees well with the prediction of Equation 1. Also shown is the improvement over a standard non-interleaved inverting charge pump. Some of the settings in this table also include an additional external resistor, R _{FLY ,} in series with C _FLY . The results show that R _FLY further reduces the voltage ripple, but at the expense of the charge pump output resistance.

In addition to output voltage ripple, the IICP also has improved radiated disturbances compared to a standard charge pump. To measure this, a 25 mm antenna was placed on the evaluation board (Figure 5) and several configurations were tested. Figure 6 shows a comparison of such a configuration with a standard non-interleaved charge pump inverter. The IICP topology reduces the noise of the first and third switching harmonics by 12 dB to 15 dB.

Figure 5. EMI test setup using the ADP5600 evaluation board.

Figure 6. Radiated electromagnetic interference, V _IN = 12 V, I _LOAD = 50 mA, C _FLY = C _OUT = 2.2 μF, f _SYNC = 500 kHz. Green = Standard, Blue = IICP.

Data converters, RF amplifiers, and RF switches require low noise power supplies. The main challenges facing power supply design in these systems are:

To illustrate the complete design and benefits of IICP, let’s consider an application that powers an RF amplifier, RF switch, and phased array beamformer. This application is covered in the ADTR1107 data sheet, from which Figure 7 is copied. This example requires several high-power positive voltage rails—in this case, the job of an inductive buck converter. Two negative voltage rails are also required: AVDD1 and VSS_SW.

Figure 7. ADAR1000 plus four ADTR1107 power rails

Figure 8. ADP5600 and LT3093 used to power AVDD1 and VSS_SW

The ADAR1000 uses AVDD1 to generate a low noise bias rail for VGG_PA and LNA_BIAS. AVDD1 is –5 V, 50 mA, and VSS_SW is the –3.3 V, <100 μA rail for the RF switches in the ADTR1107. Four ADTR1107s are used per ADAR1000, so the –3.3 V rail draws a maximum of 1 mA. Typically, the power rail for these systems is 12 V.

The ADP5600 is an ideal choice for generating –5 V, 50 mA and –3.3 V, 1 mA rails from 12 V because it achieves low input and output voltage ripple and low electromagnetic radiation interference. In addition, it can synchronize a wide range of switching frequencies, allowing the switching noise to be placed where it has the least impact on the system. Figure 8 shows the final design.

The LT3093 is an ultralow noise LDO linear regulator that supports high voltages, allowing the ADP5600 charge pump output (CPOUT) to be connected directly to its input. Its –5 V output is set by a resistor on the SET pin, and a programmable power-good pin can notify other systems when the AVDD1 rail meets requirements. The ADP5600’s LDO regulates the much lower current VSS_SW rail. Although not as low noise or as high power supply rejection ratio (PSRR) as the LT3093, it is able to provide a stable power rail for VSS_SW. The output voltage ripple of all three rails (charge pump, AVDD1, and VSS_SW) is shown in Figure 9.

Figure 9. Charge Pump Output Voltage Ripple, V _IN = 12 V, C _OUT = 10 μF (nominal), C _FLY = 2.2 μF (nominal), f _SYNC = 1 MHz (f _OSC = 500 kHz), I _LOAD = 50 mA

This article uses ADI's new product ADP5600 to build and test a complete solution and optimize it using mathematical models. Conducted emissions and electromagnetic radiation interference are also compared with standard inverting charge pumps. In some cases, the improvement is as much as 18 times compared to standard charge pump inverters, which is very important for meeting the low noise requirements of modern precision and RF systems.

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