74ACTQ16373 16-Bit Transparent Latch with 3-STATE Outputs
June 1991
Revised May 2005
74ACTQ16373
16-Bit Transparent Latch with 3-STATE Outputs
General Description
The ACTQ16373 contains sixteen non-inverting latches
with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. The flip-flops
appear transparent to the data when the Latch Enable (LE)
is HIGH. When LE is low, the data that meets the setup
time is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH, the outputs are in
high Z state. The ACTQ16373 utilizes Fairchild’s Quiet
Series
¥
technology to guarantee quiet output switching
and improved dynamic threshold performance. FACT Quiet
Series
¥
features GTO
¥
output control for superior perfor-
mance.
Features
s
Utilizes Fairchild FACT Quiet Series technology
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
s
Guaranteed pin-to-pin output skew
s
Separate control logic for each byte
s
16-bit version of the ACTQ373
s
Outputs source/sink 24 mA
s
Additional specs for Multiple Output Switching
s
Output Loading specs for both 50 pF and 250 pF loads
Ordering Code:
Order Number
74ACTQ16373SSC
74ACTQ16373MTD
Package Number
MS48A
MTD48
Package Description
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
OE
n
LE
n
I
0
–I
15
O
0
–O
15
Description
Output Enable Input (Active LOW)
Latch Enable Input
Inputs
Outputs
FACT
¥
, Quiet Series
¥
, FACT Quiet Series
¥
, and GTO
¥
are trademarks of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS010934
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74ACTQ16373
Functional Description
The ACTQ16373 contains sixteen D-type latches with 3-
STATE standard outputs. The device is byte controlled with
each byte functioning identically, but independent of the
other. Control pins can be shorted together to obtain full
16-bit operation. The following description applies to each
byte. When the Latch Enable (LE
n
) input is HIGH, data on
the D
n
enters the latches. In this condition the latches are
transparent, i.e., a latch output will change states each time
its D input changes. When LE
n
is LOW, the latches store
information that was present on the D inputs a setup time
preceding the HIGH-to-LOW transition of LE
n
. The 3-
STATE standard outputs are controlled by the Output
Enable (OE
n
) input. When OE
n
is LOW, the standard out-
puts are in the 2-state mode. When OE
n
is HIGH, the stan-
dard outputs are in the high impedance mode but this does
not interfere with entering new data into the latches.
Truth Tables
Inputs
LE
1
X
H
H
L
OE
1
H
L
L
L
Inputs
LE
2
X
H
H
L
OE
2
H
L
L
L
I
8
–I
15
X
L
H
X
I
0
–I
7
X
L
H
X
Outputs
O
0
–O
7
Z
L
H
(Previous)
Outputs
O
8
–O
15
Z
L
H
(Previous)
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial
Z High Impedance
Previous previous output prior to HIGH-to-LOW transition of LE
Logic Diagrams
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2
74ACTQ16373
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
V
I
V
O
V
O
0.5V to
7.0V
20 mA
20 mA
20 mA
20 mA
0.5V to V
CC
0.5V
50 mA
50 mA
140
q
C
65
q
C to
150
q
C
Recommended Operating
Conditions
Supply Voltage (V
CC
)
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
Minimum Input Edge Rate (
'
V/
'
t)
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
Note 1:
Absolute maximum ratings are those values beyond which dam-
age to the device may occur. The databook specifications should be met,
without exception to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT
¥
circuits outside databook specifications.
4.5V to 5.5V
0V to V
CC
0V to V
CC
0.5V
V
CC
0.5V
0.5V
V
CC
0.5V
DC Output Diode Current (I
OK
)
40
q
C to
85
q
C
125 mV/ns
DC Output Voltage (V
O
)
DC Output Source/Sink Current (I
O
)
DC V
CC
or Ground Current
per Output Pin
Junction Temperature
Storage Temperature
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
Minimum HIGH
Input Voltage
Maximum LOW
Input Voltage
Minimum HIGH
Output Voltage
Parameter
V
CC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
V
OL
Maximum LOW
Output Voltage
4.5
5.5
4.5
5.5
I
OZ
I
IN
I
CCT
I
CC
I
OLD
I
OHD
V
OLP
V
OLV
V
OHP
V
OHV
V
IHD
V
ILD
Maximum 3-STATE
Leakage Current
Maximum Input Leakage Current
Maximum I
CC
/Input
Max Quiescent Supply Current
Minimum Dynamic
Output Current (Note 3)
Quiet Output
Maximum Dynamic V
OL
Quiet Output
Minimum Dynamic V
OL
Maximum Overshoot
Minimum V
CC
Droop
Minimum HIGH Dynamic Input Voltage Level
Maximum LOW Dynamic Input Voltage Level
5.0
5.0
5.0
5.0
5.0
5.0
0.5
0.8
5.5
5.5
5.5
5.5
5.5
0.6
8.0
0.001
0.001
T
A
Typ
1.5
1.5
1.5
1.5
4.49
5.49
2.0
2.0
0.8
0.8
4.4
5.4
3.86
4.86
0.1
0.1
0.36
0.36
25
q
C
T
A
40
q
C to
85
q
C
2.0
2.0
0.8
0.8
4.4
5.4
3.76
4.76
0.1
0.1
0.44
0.44
Units
V
OUT
V
OUT
Conditions
0.1V
0.1V
Guaranteed Limits
V
V
V
or V
CC
0.1V
or V
CC
0.1V
I
OUT
V
IN
V
I
OH
I
OH
V
I
OUT
V
IN
V
I
OL
I
OL
V
I
V
O
V
I
V
I
V
IN
V
OLD
V
OHD
50
P
A
V
IL
or V
IH
24 mA
24 mA (Note 2)
50
P
A
V
IL
or V
IH
24 mA
24 mA (Note 2)
V
IL
, V
IH
V
CC
, GND
V
CC
, GND
V
CC
2.1V
V
CC
or GND
1.65V Max
3.85V Min
r
0.5
r
0.1
r
5.0
r
1.0
1.5
80.0
75
P
A
P
A
mA
P
A
mA
mA
V
V
V
V
V
V
75
Figures 1, 2
(Note 5)(Note 6)
Figures 1, 2
(Note 5)(Note 6)
Figures 1, 2
(Note 4)(Note 6)
Figures 1, 2
(Note 4)(Note 6)
(Note 4)(Note 7)
(Note 4)(Note 7)
0.5
1.0
V
OH
1.0 V
OH
1.5
V
OH
1.0 V
OH
1.8
1.7
1.2
2.0
0.8
Note 2:
All outputs loaded; thresholds associated with output under test.
Note 3:
Maximum test duration 2.0 ms; one output loaded at a time.
Note 4:
Worst case package
Note 5:
Maximum number of outputs that can switch simultaneously is n. (n
1) outputs are switched LOW and one output held LOW.
Note 6:
Maximum number of outputs that can switch simultaneously is n. (n
1) outputs are switched HIGH and one output held HIGH.
Note 7:
Max number of data inputs (n) switching, (n
1) input switching 0V to 3V. Input under test switching 3V to threshold (V
ILD
)
3
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74ACTQ16373
AC Electrical Characteristics
V
CC
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Parameter
Propagation Delay
D
n
to O
n
Propagation Delay
LE to O
n
Output Enable
Delay
Output Disable
Delay
(V)
(Note 8)
5.0
5.0
5.0
5.0
Min
3.1
2.6
3.1
2.8
2.5
2.7
2.1
2.0
T
A
C
L
25
q
C
50 pF
Typ
5.3
4.6
5.4
4.9
4.7
4.8
5.1
4.5
Max
7.9
7.3
7.9
7.3
7.4
7.5
7.9
7.4
T
A
40
q
C to
85
q
C
C
L
50 pF
Max
8.4
7.8
8.4
7.8
7.9
8.0
8.2
7.9
ns
ns
ns
ns
Units
Min
3.1
2.6
3.2
2.8
2.5
2.7
2.1
2.0
Note 8:
Voltage Range 5.0 is 5.0V
r
0.5V.
Extended AC Electrical Characteristics
T
A
V
CC
Symbol
Parameter
(V)
(Note 9)
Min
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
OSHL
(Note 14)
t
OSLH
(Note 14)
t
OST
(Note 14)
Propagation Delay
Data to Output
Propagation Delay
Latch Enable to Output
Output Enable
Time
Output Disable
Time
Pin-to-Pin Skew
HL Data to Output
Pin-to-Pin Skew
LH Data to Output
Pin-to-Pin Skew
LH/HL Data to Output
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
4.7
4.6
4.6
4.1
3.5
3.6
3.4
3.1
40
q
C to
85
q
C
C
L
50 pF
T
A
40
q
C to
85
q
C
C
L
250 pF
Units
Max
15.7
14.5
15.3
13.6
(Note 12)
(Note 13)
ns
ns
ns
ns
ns
ns
ns
(Note 11)
16 Outputs Switching
(Note 10)
Max
12.7
10.6
13.3
10.4
10.4
10.9
8.5
8.1
1.3
2.1
4.0
Min
6.6
6.4
6.3
5.8
Note 9:
Voltage Range 5.0 is 5.0V
r
0.5V.
Note 10:
This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 11:
This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load. This specification pertains to single output switching only.
Note 12:
3-STATE delays are load dominated and have been excluded from the datasheet.
Note 13:
The Output Disable Time is dominated by the RC Network (500
:
, 250 pF) on the output and has been excluded from the datasheet.
Note 14:
Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH-to-LOW (t
OSHL
), LOW-to-HIGH (t
OSLH
), or any combination switching LOW-to-HIGH and/or HIGH-
to-LOW (t
OST
).
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4
74ACTQ16373
AC Operating Requirements
V
CC
Symbol
t
S
t
H
t
W
Parameter
Setup Time, HIGH or LOW,
Input to Clock
Hold Time, HIGH or LOW
Input to Clock
CS Pulse Width,
HIGH or LOW
Note 15:
Voltage Range 5.0 is 5.0V
r
0.5V
T
A
C
L
25
q
C
50 pF
T
A
40
q
C to
85
q
C
C
L
50 pF
Units
(V)
(Note 15)
5.0
5.0
5.0
Guaranteed Minimum
3.0
1.5
4.0
3.0
1.5
4.0
ns
ns
ns
Capacitance
Symbol
C
IN
C
PD
Parameter
Input Capacitance
Power Dissipation Capacitance
Typ
4.5
30
Units
pF
pF
Conditions
V
CC
V
CC
5.0V
5.0V
5
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