ATF1502ASVL-25JI44 datasheet, PDF

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ATF1502ASVL-25JI44: DescriptionEE PLD, 25ns, 32-Cell, CMOS, PQCC44, PLASTIC, MS-018AC, LCC-44; CategoryProgrammable logic devices Programmable logic; File Size371KB，18 Pages; ManufacturerAtmel (Microchip)

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ATF1502ASVL-25JI44 Overview

EE PLD, 25ns, 32-Cell, CMOS, PQCC44, PLASTIC, MS-018AC, LCC-44

ATF1502ASVL-25JI44 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Atmel (Microchip)
Parts packaging code	LPCC
package instruction	PLASTIC, MS-018AC, LCC-44
Contacts	44
Reach Compliance Code	not_compliant
Other features	YES
maximum clock frequency	60 MHz
In-system programmable	YES
JESD-30 code	S-PQCC-J44
JESD-609 code	e0
JTAG BST	YES
length	16.5862 mm
Humidity sensitivity level	2
Dedicated input times
Number of I/O lines	32
Number of macro cells	32
Number of terminals	44
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	0 DEDICATED INPUTS, 32 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC44,.7SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	225
power supply	3 V
Programmable logic type	EE PLD
propagation delay	25 ns
Certification status	Not Qualified
Maximum seat height	4.57 mm
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	16.5862 mm

ATF1502ASVL-25JI44 Preview

Features

•

High-density, High-performance, Electrically-erasable Complex Programmable

Logic Device

– 3.0 or 3.6V Operating Range

– 32 Macrocells

– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell

– 44 Pins

– 15 ns Maximum Pin-to-pin Delay

– Registered Operation up to 77 MHz

– Enhanced Routing Resources

In-System Programmability (ISP) via JTAG

Flexible Logic Macrocell

– D/T Latch Configurable Flip-flops

– Global and Individual Register Control Signals

– Global and Individual Output Enable

– Programmable Output Slew Rate

– Programmable Output Open Collector Option

– Maximum Logic Utilization by Burying a Register with a COM Output

Advanced Power Management Features

– Automatic 5 µA Standby for “L” Version

– Pin-controlled 100 µA Standby Mode

– Programmable Pin-keeper Inputs and I/Os

– Reduced-power Feature per Macrocell

Available in Commercial and Industrial Temperature Ranges

Available in 44-lead PLCC and TQFP

Advanced EEPROM Technology

– 100% Tested

– Completely Reprogrammable

– 10,000 Program/Erase Cycles

– 20-year Data Retention

– 2000V ESD Protection

– 200 mA Latch-up Immunity

JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported

PCI-compliant

Security Fuse Feature

•

High-

performance

EEPROM CPLD

ATF1502ASV

ATF1502ASVL

•

Enhanced Features

•

Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)

Output Enable Product Terms

D Latch Mode

Combinatorial Output with Registered Feedback within Any Macrocell

Three Global Clock Pins

ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O

Fast Registered Input from Product Term

Programmable “Pin-keeper” Option

Power-up Reset Option

Pull-up Option on JTAG Pins TMS and TDI

Advanced Power Management Features

– Edge-controlled Power-down “L”

– Individual Macrocell Power Option

– Disable ITD on Global Clocks, Inputs and I/O

Rev. 1615D–03/01

44-lead TQFP

Top View

I/O

VCC

I/OE2/GCK2

GCLR/I

I/OE1

GCK1/I

GND

GCK3

I/O

44-lead PLCC

Top View

I/O

VCC

GCK2/OE2/I

GCLR/I

OE1/I

GCK1/I

GND

I/O/GCLK3

I/O

I/O/TDO

I/O

VCC

I/O

I/O/TCK

I/O

GND

I/O

I/O/TDI

I/O

GND

PD1/I/O

I/O

TMS/I/O

I/O

VCC

I/O

Description

The ATF1502ASV is a high-performance, high-density

complex programmable logic device (CPLD) that utilizes

Atmel’s proven electrically-erasable technology. With 32

logic macrocells and up to 36 inputs, it easily integrates

logic from several TTL, SSI, MSI, LSI and classic PLDs.

The ATF1502ASV’s enhanced routing switch matrices

increase usable gate count and the odds of successful pin-

locked design modifications.

The ATF1502ASV has up to 32 bi-directional I/O pins and

four dedicated input pins, depending on the type of device

package selected. Each dedicated pin can also serve as a

global control signal, register clock, register reset or output

enable. Each of these control signals can be selected for

use individually within each macrocell.

ATF1502ASV(L)

I/O

GND

VCC

I/O

PD2/I/O

I/O

GND

VCC

I/O

PD2/I/O

I/O

TDI/I/O

I/O

GND

PD1/I/O

I/O

I/O/TMS

I/O

VCC

I/O

I/O/TDO

I/O

VCC

I/O

I/O/TCK

I/O

GND

I/O

ATF1502ASV(L)

Block Diagram

Each of the 32 macrocells generates a buried feedback

that goes to the global bus. Each input and I/O pin also

feeds into the global bus. The switch matrix in each logic

block then selects 40 individual signals from the global bus.

Each macrocell also generates a foldback logic term that-

goes to a regional bus. Cascade logic between macrocells

in the ATF1502ASV allows fast, efficient generation of

complex logic functions. The ATF1502ASV contains four

such logic chains, each capable of creating sum term logic

with a fan-in of up to 40 product terms.

The ATF1502ASV macrocell, shown in Figure 1, is flexible

enough to support highly complex logic functions operating

at high speed. The macrocell consists of five sections:

product terms and product term select multiplexer,

OR/XOR/CASCADE logic, a flip-flop, output select and

enable, and logic array inputs.

Unused product terms are automatically disabled by the

compiler to decrease power consumption. A security fuse,

when programmed, protects the contents of the

ATF1502ASV. Two bytes (16 bits) of User Signature are

accessible to the user for purposes such as storing project

name, part number, revision or date. The User Signature is

accessible regardless of the state of the security fuse.

The ATF1502ASV device is an in-system programmable

(ISP) device. It uses the industry standard 4-pin JTAG

interface (IEEE Std. 1149.1), and is fully compliant with

JTAG’s Boundary-scan Description Language (BSDL). ISP

allows the device to be programmed without removing it

from the printed circuit board. In addition to simplifying the

manufacturing flow, ISP also allows design modifications to

be made in the field via software.

Figure 1.

ATF1502ASV Macrocell

Product Terms and Select Mux

Each ATF1502ASV macrocell has five product terms. Each

product term receives as its inputs all signals from both the

global bus and regional bus.

The product term select multiplexer (PTMUX) allocates the

five product terms as needed to the macrocell logic gates

and control signals. The PTMUX programming is deter-

mined by the design compiler, which selects the optimum

macrocell configuration.

OR/XOR/CASCADE Logic

The ATF1502ASV’s logic structure is designed to efficiently

support all types of logic. Within a single macrocell, all the

product terms can be routed to the OR gate, creating a

5-input AND/OR sum term. With the addition of the CASIN

from neighboring macrocells, this can be expanded to as

many as 40 product terms with little additional delay.

The macrocell’s XOR gate allows efficient implementation

of compare and arithmetic functions. One input to the XOR

comes from the OR sum term. The other XOR input can be

a product term or a fixed high or low level. For combinato-

rial outputs, the fixed level input allows polarity selection.

For registered functions, the fixed levels allow DeMorgan

minimization of product terms. The XOR gate is also used

to emulate T- and JK-type flip-flops.

Flip-flop

The ATF1502ASV’s flip-flop has very flexible data and con-

trol functions. The data input can come from either the XOR

gate, from a separate product term or directly from the I/O

pin. Selecting the separate product term allows creation of

a buried registered feedback within a combinatorial output

macrocell. (This feature is automatically implemented by

the fitter software). In addition to D, T, JK and SR opera-

tion, the flip-flop can also be configured as a flow-through

latch. In this mode, data passes through when the clock is

high and is latched when the clock is low.

The clock itself can be either one of the Global CLK signals

(GCK[0 : 2]) or an individual product term. The flip-flop

changes state on the clock’s rising edge. When the GCK

signal is used as the clock, one of the macrocell product

terms can be selected as a clock enable. When the clock

enable function is active and the enable signal (product

term) is low, all clock edges are ignored. The flip-flop’s

asynchronous reset signal (AR) can be either the Global

Clear (GCLEAR), a product term, or always off. AR can

also be a logic OR of GCLEAR with a product term. The

asynchronous preset (AP) can be a product term or always

off.

ATF1502ASV(L)

ATF1502ASV(L)

Output Select and Enable

The ATF1502ASV macrocell output can be selected as

registered or combinatorial. The buried feedback signal can

be either combinatorial or registered signal regardless of

whether the output is combinatorial or registered.

The output enable multiplexer (MOE) controls the output

enable signals. Any buffer can be permanently enabled for

simple output operation. Buffers can also be permanently

disabled to allow use of the pin as an input. In this configu-

ration all the macrocell resources are still available,

including the buried feedback, expander and CASCADE

logic. The output enable for each macrocell can be

selected as either of the two dedicated OE input pins, as an

I/O pin configured as an input, or as an individual product

term.

Global Bus/Switch Matrix

The global bus contains all input and I/O pin signals as well

as the buried feedback signal from all 32 macrocells. The

switch matrix in each logic block receives as its inputs all

signals from the global bus. Under software control, up to

40 of these signals can be selected as inputs to the logic

block.

Foldback Bus

Each macrocell also generates a foldback product term.

This signal goes to the regional bus and is available to four

macrocells. The foldback is an inverse polarity of one of the

macrocell’s product terms. The four foldback terms in each

region allow generation of high fan-in sum terms (up to nine

product terms) with little additional delay.

Input Diagram

I/O Diagram

Speed/Power Management

The ATF1502ASV has several built-in speed and power

management features. The ATF1502ASV contains circuitry

that automatically puts the device into a low-power standby

mode when no logic transitions are occurring. This not only

reduces power consumption during inactive periods, but

also provides proportional power savings for most applica-

tions running at system speeds below 5 MHz. This feature

may be selected as a design option.

To further reduce power, each ATF1502ASV macrocell has

a reduced-power bit feature. To reduce power consumption

this feature may be actived (by changing the default value

of OFF to ON) for any or all macrocells.

Programmable Pin-keeper Option for

Inputs and I/Os

The ATF1502ASV offers the option of programming all

input and I/O pins so that pin-keeper circuits can be uti-

lized. When any pin is driven high or low and then

subsequently left floating, it will stay at that previous high or

low level. This circuitry prevents unused input and I/O lines

from floating to intermediate voltage levels, which causes

unnecessary power consumption and system noise. The

keeper circuits eliminate the need for external pull-up resis-

tors and eliminate their DC power consumption.

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ATF1502ASVL-25JI44 Related Products

	ATF1502ASVL-25JI44	ATF1502ASVL-25JC44	ATF1502ASVL-25AI44	ATF1502ASVL-25AC44
Description	EE PLD, 25ns, 32-Cell, CMOS, PQCC44, PLASTIC, MS-018AC, LCC-44	EE PLD, 25ns, 32-Cell, CMOS, PQCC44, PLASTIC, MS-018AC, LCC-44	EE PLD, 25ns, 32-Cell, CMOS, PQFP44, 1 MM HEIGHT, PLASTIC, TQFP-44	EE PLD, 25ns, 32-Cell, CMOS, PQFP44, 1 MM HEIGHT, PLASTIC, TQFP-44
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible
Maker	Atmel (Microchip)	Atmel (Microchip)	Atmel (Microchip)	Atmel (Microchip)
Parts packaging code	LPCC	LPCC	QFP	QFP
package instruction	PLASTIC, MS-018AC, LCC-44	PLASTIC, MS-018AC, LCC-44	1 MM HEIGHT, PLASTIC, TQFP-44	1 MM HEIGHT, PLASTIC, TQFP-44
Contacts	44	44	44	44
Reach Compliance Code	not_compliant	not_compliant	not_compliant	_compli
Other features	YES	YES	YES	YES
maximum clock frequency	60 MHz	60 MHz	60 MHz	60 MHz
In-system programmable	YES	YES	YES	YES
JESD-30 code	S-PQCC-J44	S-PQCC-J44	S-PQFP-G44	S-PQFP-G44
JESD-609 code	e0	e0	e0	e0
JTAG BST	YES	YES	YES	YES
length	16.5862 mm	16.5862 mm	10 mm	10 mm
Number of I/O lines	32	32	32	32
Number of macro cells	32	32	32	32
Number of terminals	44	44	44	44
Maximum operating temperature	85 °C	70 °C	85 °C	70 °C
organize	0 DEDICATED INPUTS, 32 I/O	0 DEDICATED INPUTS, 32 I/O	0 DEDICATED INPUTS, 32 I/O	0 DEDICATED INPUTS, 32 I/O
Output function	MACROCELL	MACROCELL	MACROCELL	MACROCELL
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	QCCJ	QCCJ	TQFP	TQFP
Encapsulate equivalent code	LDCC44,.7SQ	LDCC44,.7SQ	QFP44,.47SQ,32	QFP44,.47SQ,32
Package shape	SQUARE	SQUARE	SQUARE	SQUARE
Package form	CHIP CARRIER	CHIP CARRIER	FLATPACK, THIN PROFILE	FLATPACK, THIN PROFILE
Peak Reflow Temperature (Celsius)	225	225	240	240
power supply	3 V	3 V	3 V	3 V
Programmable logic type	EE PLD	EE PLD	EE PLD	EE PLD
propagation delay	25 ns	25 ns	25 ns	25 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	4.57 mm	4.57 mm	1.2 mm	1.2 mm
Maximum supply voltage	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage	3 V	3 V	3 V	3 V
Nominal supply voltage	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	J BEND	J BEND	GULL WING	GULL WING
Terminal pitch	1.27 mm	1.27 mm	0.8 mm	0.8 mm
Terminal location	QUAD	QUAD	QUAD	QUAD
Maximum time at peak reflow temperature	30	30	30	30
width	16.5862 mm	16.5862 mm	10 mm	10 mm

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