CD74ACT112ME4 datasheet, PDF - EEWORLD Datasheet

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CD74ACT112ME4: DescriptionDual Negative-Edge Triggered J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125; Categorylogic logic; File Size805KB，13 Pages; ManufacturerTexas Instruments; Websitehttp://www.ti.com.cn/; Environmental Compliance

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CD74ACT112ME4 Overview

Dual Negative-Edge Triggered J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125

CD74ACT112ME4 Parametric

Parameter Name	Attribute value
Brand Name	Texas Instruments
Is it Rohs certified?	conform to
Maker	Texas Instruments
Parts packaging code	SOIC
package instruction	SOP, SOP16,.25
Contacts	16
Reach Compliance Code	compli
Factory Lead Time	1 week
series	ACT
JESD-30 code	R-PDSO-G16
JESD-609 code	e4
length	9.9 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	J-K FLIP-FLOP
Maximum Frequency@Nom-Su	100000000 Hz
MaximumI(ol)	0.024 A
Humidity sensitivity level	1
Number of digits	2
Number of functions	2
Number of terminals	16
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Output polarity	COMPLEMENTARY
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP16,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
method of packing	TUBE
Peak Reflow Temperature (Celsius)	260
power supply	5 V
propagation delay (tpd)	10.3 ns
Certification status	Not Qualified
Maximum seat height	1.75 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
Trigger type	NEGATIVE EDGE
width	3.9 mm
minfmax	100 MHz

CD74ACT112ME4 Related Products

	CD74ACT112ME4	CD74ACT112M	CD74ACT112MG4	CD74ACT112M96
Description	Dual Negative-Edge Triggered J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125	Dual Negative-Edge Triggered J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125	Dual Negative-Edge Triggered J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125	Dual Negative-Edge Triggered J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125
Brand Name	Texas Instruments	Texas Instruments	Texas Instruments	Texas Instruments
Is it Rohs certified?	conform to	conform to	conform to	conform to
Parts packaging code	SOIC	SOIC	SOIC	SOIC
package instruction	SOP, SOP16,.25	SOP, SOP16,.25	SOP, SOP16,.25	GREEN, PLASTIC, MS-012AC, SOIC-16
Contacts	16	16	16	16
Reach Compliance Code	compli	compli	compli	compli
Factory Lead Time	1 week	1 week	6 weeks	1 week
series	ACT	ACT	ACT	ACT
JESD-30 code	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16
JESD-609 code	e4	e4	e4	e4
length	9.9 mm	9.9 mm	9.9 mm	9.9 mm
Load capacitance (CL)	50 pF	50 pF	50 pF	50 pF
Logic integrated circuit type	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP
Maximum Frequency@Nom-Su	100000000 Hz	100000000 Hz	100000000 Hz	100000000 Hz
MaximumI(ol)	0.024 A	0.024 A	0.024 A	0.024 A
Humidity sensitivity level	1	1	1	1
Number of digits	2	2	2	2
Number of functions	2	2	2	2
Number of terminals	16	16	16	16
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-55 °C	-55 °C	-55 °C	-55 °C
Output polarity	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	SOP	SOP	SOP
Encapsulate equivalent code	SOP16,.25	SOP16,.25	SOP16,.25	SOP16,.25
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE
method of packing	TUBE	TUBE	TUBE	TR
Peak Reflow Temperature (Celsius)	260	260	260	260
power supply	5 V	5 V	5 V	5 V
propagation delay (tpd)	10.3 ns	10.3 ns	10.3 ns	10.3 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.75 mm	1.75 mm	1.75 mm	1.75 mm
Maximum supply voltage (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage (Vsup)	4.5 V	4.5 V	4.5 V	4.5 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V
surface mount	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	MILITARY	MILITARY	MILITARY	MILITARY
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	1.27 mm	1.27 mm	1.27 mm	1.27 mm
Terminal location	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
Trigger type	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE
width	3.9 mm	3.91 mm	3.9 mm	3.91 mm
minfmax	100 MHz	100 MHz	100 MHz	100 MHz
Maker	Texas Instruments	-	Texas Instruments	Texas Instruments
Is it lead-free?	-	Lead free	Lead free	Lead free
Maximum supply current (ICC)	-	0.04 mA	0.08 mA	0.08 mA
Prop。Delay @ Nom-Su	-	11.1 ns	11.1 ns	11.1 ns
Schmitt trigger	-	N	N	N

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