Digital control frequency division circuit composed of MC4018

As shown in the figure is the digital control frequency division circuit.

Figure (a) is the principle diagram of the digital control divider. It can achieve any frequency division coefficient and output a symmetrical square wave. For any even number N, it can be written as N=2M, and for any odd number N, it can be written as N=2M 1. If N is expressed in binary, the lowest binary bit can be discarded to get M, so the binary number can be used to control the frequency division number. Therefore, for a given N, an M divider can be designed. For example, N=181, then the M added to the divider is 90.

Figure (b) is an actual application circuit. The digital control logic state depends on whether N is an even number or an odd number. When N is an even number, the lowest bit LSB of the binary number = "0", so the odd-even control input is "0", and the outputs of gates G3 and G4 are clamped in the "1" state, so FF2~FF4 is a shift register. The output of FF4 is a symmetrical square wave, and it is synchronized with the input signal frequency fin.