What are the parts of the fpga design process

FPGA is a programmable chip, so the design method of FPGA includes two parts: hardware design and software design. The hardware includes FPGA chip circuits, memory, input and output interface circuits and other devices. The software is the corresponding VHDL program and VerilogHDL program. FPGA adopts a top-down design method, starting with system-level design, and then gradually divided into secondary units and tertiary units until it is known that the basic logic unit or IP core can be directly operated. Usually, the design process includes the following steps:

1. Function Definition/Equipment Selection

Before the FPGA design project begins, there must be a definition of system functions and a division of modules. In addition, according to the task requirements, such as system functions and complexity, the speed of work and the resources, cost and distribution of the wires should be balanced. Then choose the right design scheme and the appropriate device type.

2.Design input

Design input includes schematic input and hardware description language input. Schematic input is intuitive, but not easy to simulate. In addition, it is inefficient and difficult to maintain. It is not conducive to module construction and reuse. The main disadvantage is its poor portability. When the chip is upgraded, all schematics need to be changed. Hardware languages ​​include VHDL, VerilogHDL, SystemC, etc. The common feature of hardware description language input is that the language is independent of chip technology, which is conducive to top-down design and easy to partition and transplant modules. They have good portability, powerful logic description and simulation capabilities.

3. Functional simulation

Functional simulation, also known as pre-simulation, is used to verify the logic function of the user-designed circuit before compilation. At this time, there is no delay information, only the initial detection of the function.

4. Synthesis

The so-called synthesis is to transform the description of the upper abstract level into the description of the lower level. Integrated optimization can optimize the goals and requirements based on the hierarchical design plane generated by logical connections, and implement FPGA layout and routing software. At the current level, synthesis compiles the design input into a logical connection network table, which is composed of basic logic units such as AND gates, extraction gates, inverters, RAMs, flip-flops, etc. It is not a real gate circuit.

5. Post synthesis simulation

The purpose of simulation is to check whether the synthesis result is consistent with the original design. In simulation, when the standard delay file generated by synthesis is de-marked into the synthesis simulation model, the influence of gate delay can be estimated. However, this step cannot estimate the delay of the line, so there is still a certain gap with the actual situation after routing, which is not very accurate.

6. Implement and layout routing

Placement and routing can be understood as using the implementation tool to map logic to the resources of the target device structure to determine the best placement of the logic, and select the logic to connect to the routing channels connected to the input/output functions and generate appropriate files (such as configuration files and related reports). The implementation method is to configure the logic network table generated by synthesis on a specific FPGA chip.

7. Timing simulation

Timing simulation, also known as post-simulation, refers to annotating the delay information of layout and routing back to the design network table to detect whether there are any timing irregularities (i.e., failure to meet the timing constraints or the device's inherent timing rules, such as setup time, maintenance time, etc.). The delay information contained in the timing simulation is the most complete and accurate, and can better reflect the actual operation of the chip.

8. Board-level simulation and verification

Board-level simulation is mainly used for high-speed circuit design. It analyzes the signal integrity, electromagnetic interference and other characteristics of high-speed systems, and is generally simulated and verified by third-party tools.

9. Chip programming and debugging

The last step of the design is chip programming and debugging. Chip programming is the generation of data files (bitstream file/bitstream generation). Then the program data is downloaded to the FPGA chip. Logic analyzer is the main debugging tool for FPGA design. But it requires a lot of test pins, and LA is expensive. At present, mainstream FPGA chip manufacturers all provide embedded online logic analyzers.