Image sensor interface circuit diagram based on video surveillance system

Circuit principle: The interface between OV9650 and the processor includes three parts: SCCB interface, data output interface and control interface. The SCCB interface plays the role of transmitting the initialization OV9650 internal register parameters provided by the processor. Its data line SIOD and clock line SI-OC are equivalent to SDA and SCL in the I2C bus. In other words, SC-CB functions as an I2C bus. OV9650 is the slave device of the I2C bus, and S3C2440 is the corresponding master device. The I2 C bus uses serial mode to transmit byte data from high bit to low bit. After each byte is transmitted, the main controller sets SDA to high level and releases it, waiting for the slave device to send a confirmation signal. OV9650 has a built-in 10-bit A/D converter, corresponding to 10 data output ports D[0: 9]. The format of the output image data can be 10-bit raw RAW, RGB or 8-bit RGB/YCbCr converted by internal DSP. The CAM IF unit of the microprocessor chip S3C2440 selected for this system supports the 8-bit YU V/YCbCr format, so the data interface D[9: 2] of OV9650 needs to be connected to the data port CAMDAT A[7: 0] of the CAM IF. connect. The XVCLK of OV9650 is used to receive the 24 MHz working clock output by the CPU. Three clock signals, including the frame synchronization signal VSYNC, the horizontal synchronization signal HREF, and the pixel clock signal PCLK generated internally by the OV9650, are transmitted to the ARM chip for controlling image acquisition. Each VSYN C pulse indicates the beginning of a frame of image data acquisition. The high level of HREF indicates the acquisition of a line of image data. The image sensor collects one byte of data in sequence from left to right during each PCLK pulse. Until all the image data of one frame is collected. The camera uses the CAM130 module, and the image sensor is OV9650 . The schematic diagram and interface circuit of this part are shown in the figure below.