Video surveillance system terminal circuit diagram

Video surveillance systems are increasingly entering people's lives, and system energy saving is also an important parameter that electronic systems must consider. For an occasion where few people come and go, it is not only unnecessary to use uninterrupted real-time monitoring, but also waste a lot of power. In response to this situation, this article designs an unattended intelligent monitoring terminal. When no one enters the monitoring area, the monitoring terminal is in a low-energy sleep state; when the infrared sensor detects that someone has entered the monitoring area, the terminal wakes up and starts taking pictures, and at the same time transmits the processed video signal to the monitoring center through the network. The personnel on duty at the center provide the basis for judgment. For occasions with fewer people entering and exiting, the use of this monitoring terminal can effectively reduce system energy consumption, reduce the amount of data transmitted and saved, and will not miss monitoring objects.

Infrared sensing signal processing module

In order to save power, this terminal uses infrared sensors to detect whether people enter the monitoring area. Only when someone enters the monitoring area, the terminal enters the image collection, processing, and transmission state. This design uses the BISS0001 chip as the core component of pyroelectric infrared sensing signal processing. Its application circuit is shown in Figure 1.

Figure 1 Infrared signal processing circuit

In Figure 1, 7805 is a three-terminal voltage stabilizing integrated circuit that provides power for the signal processing circuit. The 9th pin of the BISS0001 chip is the input pin of the trigger control signal Vc. The input voltage should be guaranteed during operation. This can be achieved by adjusting the resistor R3. When a pedestrian enters the monitoring area, the pyroelectric infrared sensor PIR converts the detected infrared rays emitted by the human body into an electrical signal and sends it to the inside of BISS0001. The signal is processed by BISS0001 and output through pin 2. The output Vo is low power. level to high transition. If BISS0001 works in a valid state and cannot be triggered repeatedly (that is, S1 is connected to a low level in Figure 1), the duration of the high level is Ts (Ts=49 152 R1C1). At the end of the Ts period, the output Vo is instantaneous From high level to low level and blocked for Ti (Ti =24R2C2) time; for the case where the valid state can be triggered repeatedly (that is, S1 is connected to high level in Figure 1), if within the previous Ts time period, The change in the input causes the output valid state to be triggered again, then the Vo high-level signal will continue for another Tx duration from this moment on, before converting to low level and entering the blocking time Ti. During the blocking time, even due to load switching, The interference introduced will not change the state of the output Vo. In this design, S1 is connected to a high level, and the output signal Vo of the infrared sensing signal processing circuit is used as the external interrupt signal of the DM642, and is also used as the power-saving mode input control signal of the TVP5150 chip, as shown in Figure 1.

Image acquisition module

For the image acquisition module, this design uses TI's TVP5150 as the decoding chip. TVP5150 is an ultra-low-power decoding chip, with a power consumption of only 113 mW during normal operation and 1 mW in power-saving mode. It supports PAL/NTSC/SECAM and other formats. It can convert the data collected by the camera into The analog image signal is converted into an ITU-R BT.656 digital signal in YUV4:2:2 format. It can receive 2 channels of composite video signals (CVBS) or 1 channel of S-Video signals. The internal register can be set through the I2C bus and the output can be selected. 8-bit 4:2:2 ITU-R BT.656 digital signal (sync signal embedded), and 8-bit 4:2:2 ITU-R BT.601 signal (sync signal separated, separate pin output). The hardware connection between TVP5150 and DM642 is shown in Figure 2.

Figure 2 TVP5150 and DM642 hardware connection diagram

AIP1A and AIP1B of the TVP5150 chip are the input terminals of analog signals. This pin needs to be connected to a filter capacitor of 0.1~1 μF. HSYNC is the output pin of the horizontal synchronization signal. Since this design uses the ITU-R BT.656 format with embedded synchronization signal, this pin is not connected to the DM642 related pins. The PND pin is the control signal input terminal of the power-saving mode. It is active at low level and is connected to the output signal Vo of the infrared sensing signal processing circuit. When there are no pedestrians walking in the monitoring area, Vo is low level, which will make the TVP5150 chip Enter power saving mode. YOUT[6:0] is the BT.656/YUV data output pin, YOUT /I2CSEL is the 7th bit of the BT.656/YUV data, and is also the I2C interface device address setting bit. The TVP5150 device address is connected to the I2CSEL pin The pull-up resistor or pull-down resistor is determined. The mapping relationship between the status of the I2CSEL pin and the device address is shown in Table 1. The address of the slave TVP5150 is required during the response process of DM642 and TVP5150. SCL and SDA are the serial clock and data pins of the I2C interface respectively. DM642 accesses the internal registers of TVP5150 through the I2C bus. VP0D [19:0] of the DM642 chip is the data bus pin of the video port VP0. VP0D [8:2] is multiplexed with the multi-channel serial port McBSP0 pin. In order to configure VP0D [8:2] as the VP0 pin For the low-order data pin, you need to set the VP0EN position 1.VP0CLK0 in the PERCFG register as the external pixel clock input pin and connect it to the pixel clock output pin PCLK/SCLK of the video decoding chip TVP5150.