How to build a "full-power" chip

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How to build a "full-power" chip [Copy link]

Chip design faces a variety of challenges in many aspects, which require network and system design expertise as well as chip technology to solve. Ultimately, customers always want to reduce total system costs and improve product performance and profitability. Therefore, whether companies that design network and system chips can successfully meet customer needs will determine their future development in the next few years.

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　　Today, the main problem facing designers is how to build a single chip with full functionality to handle a variety of applications. Building a full-function chip is expensive and requires considerable effort, far more than building a small chip. Therefore, it is more important than ever to ensure the success rate of the first design, otherwise it may lose a lot of investment and seriously reduce the return on investment of chip design.

　　At the same time, the integration of functions of chips with different functions is expected to eventually reduce the number of chips. For example, designers have to solve the problem of integrating memory chip technology with mobile phone chip technology, and integrating radio frequency technology and digital signal processor (DSP) technology in mobile phones.

　　In these cases, the problem we need to solve can be summarized as how to make different smart blocks work together, which is equivalent to achieving integration of different smart blocks, in other words, how to maximize chip efficiency and performance levels.

　　Another important development trend is that we are moving from small chip design to complex architecture and system design, which often includes multiple chips. This development trend is also a natural result of the development of single-function chips to SoCs. Today, single chips often have functions that were previously only possible with the entire system. We define, design, and build chips from a holistic view of the overall system architecture. In this architecture, questions such as how to design a reference board platform are becoming increasingly common. Therefore, we design at two levels, namely the chip and the system.

　　At the same time, the requirements and emphasis on chip speed have been reduced because performance is the most important factor. The speed of the chip has always been the main design issue. However, speed is now just one of a growing number of variables, factors, and characteristics that chip designers must consider. For example, DSP manufacturers used to promote DSP speed as the first factor, but now they have to take chip size and interoperability with other chips seriously, which is driven by customer needs.

　　Chip designers have proven that they can continue to increase chip clock speeds. However, power consumption continues to increase with speed, which makes chip packages and system devices hotter and hotter. Despite the increase in bandwidth and the increase in functional features, the power consumption requirements of devices are still the same as they were ten years ago. Therefore, despite the wide and deep development of SoC integration technology, power consumption will continue to exist for a long time.

　　For example, in network processor chip technology, the goal is to ensure that the chip has appropriate traffic management and quality of service functions, while ensuring that the chip is fast and highly integrated. Therefore, chip designers must launch chips with more diverse functions and smaller form factors, while ensuring that they are faster without causing more power consumption. As a result, we are now facing a multi-faceted design challenge for basic, relatively simple chip designs in the past.

　　The increasing importance of channel density has also had an impact on chip design. Channel density is related to the amount of voice, data and video signals that can be accommodated in a given chip space. In Gigabit Ethernet, network processor and DSP applications, it is critical to understand how to increase the number of channels integrated into the chip. We need to design powerful and reliable chips, and increase the amount of voice, data and video signals that can be accommodated in a given chip space. In some cases, it is as important as the clock speed of the chip to increase the amount of voice, data and video signals that can be accommodated in a given chip space. In fact, ensuring low power consumption is often the bottleneck to maximizing channel density.

　　In wireless networks, it is increasingly common to design systems and chips that integrate a variety of different protocols and standards into as few systems and chips as possible. For example, we use a single chip to integrate asynchronous transfer mode and Internet protocol technologies on a single network.

　　In the field of Ethernet chips, the current trend is still to design telecommunications and enterprise systems using highly integrated SoC chips. In this case, the challenge we encounter is how to integrate network processing technology and high-density Gigabit Ethernet technology on the same platform, which is necessary to achieve carrier-class features on low-cost Ethernet infrastructure.

　　At the same time, software is playing an increasingly important strategic technology role in chip design. In short, chip designers should realize that software is an important factor in differentiating their products, and the breadth of related design work is and will continue to increase. Designers now face software design challenges that are much greater than in the past.

　　Given the above situation, chip design faces a variety of different challenges in many aspects, which require network and system design expertise as well as chip technology to solve. Ultimately, customers always want to reduce total system costs and improve product performance and profitability. Therefore, the success of companies designing network and system chips in meeting customer needs will determine their future development in the next few years.

Source: EDN Electronic Design Technology