Design of software architecture for multi-signal parallel processing based on DSP/BIOS

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Design of software architecture for multi-signal parallel processing based on DSP/BIOS [Copy link]

DSP/BIOS is a real-time operating system launched by TI, which is integrated into the CCS (Code Composer Studio) development environment. DSP/BIOS adopts a static configuration strategy. By removing the running code, it can minimize the storage space of the target program, optimize the internal data structure, and detect errors earlier by confirming the ownership of the object before the program is executed. It can meet the debugging and performance analysis of DSP runtime. Using DSP/BIOS can quickly write efficient programs and greatly simplify the development and debugging of DSP applications. DSP/BIOS is a set of system module application program interface APIs that can be repeatedly called, divided into system module System, auxiliary module Instrumentation, scheduling module Scheduling, synchronization module Synchronization, communication module Input/Output and configuration module CSL. The system module mainly completes chip model confirmation, endian mode configuration, main frequency configuration, chip cashe space division and memory space allocation. The auxiliary module Instrumentation is mainly responsible for message printing, event log and information tracking. The scheduling module is the core function of DSP/BIOS, which can be subdivided into timing management CLK, periodic interrupt management PRD, hard interrupt management HWI, soft interrupt management SWI, task management TSK and idle task management IDL. CLK controls the 32-bit real-time logic clock in the chip and is responsible for setting the PRD cycle. PRD manages cycle objects and triggers the cycle execution of the application. It is a special SWI. HWI manages hardware interrupts and is mainly responsible for the data interaction between DSP and peripherals. The interrupt service program should be as short and precise as possible. SWI is a non-blocking preemptive type. SWI tasks can only be pre-defined when the program is compiled. TSK is a blocking preemptive type and supports dynamic generation of tasks. IDL manages the sleep function. The sleep function is started when the target system program has no higher priority function running. It is a special TSK. The synchronization module is responsible for the exchange and transmission of information between various scheduling modules to ensure synchronization and mutual exclusion between scheduling modules. The communication module allows the application to exchange data between the target system and the host. The configuration module is responsible for the configuration of the underlying hardware of the chip. In addition, DSP/BIOS also has plug-ins to support real-time analysis, program tracking and performance monitoring. DSP_BIOS的多信号并行处理软件架构设计.pdf (139.86 KB, downloads: 6)

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