Digital signal processing block diagram in XCD2500BQ

In the VCD/DVD player, the digital signal processing circuit DSP circuit is also part of the servo system. The preamplifier circuit
amplifies the signal read by the laser head and then sends the RF signal to the DSP circuit for digital processing. At the same time, from
The rotation error of the spindle motor is also detected in the digital signal , which is converted into a drive signal to control the spindle motor after processing, so that the spindle motor
rotates according to the requirement of constant linear speed. Therefore, the spindle motor servo circuit is also called CLV servo, and CLV means constant line speed. The meaning of speed (Constant Linear Velocity).
Integrated circuits such as CXD2500 and CXD2545 are integrated circuits designed for this purpose.
    Figure 28-4 shows the circuit block diagram of CXD2500BQ. The circuit mainly includes: 32 K buffer RAM, voltage controlled oscillator,
asymmetric corrector, phase locked loop, digital audio interface, address signal generator, error correction circuit, Variable beat control circuit, EFM demodulation circuit
, digital signal output circuit, spindle motor CLV processor servo status detection and control circuit, etc.
    V CD discs perform 8-14bit conversion of digital signals before recording, or 8-14bit modulation, or EFM modulation. This is
a method adopted to reduce the bit error rate. The digital signal read by the laser head is the EFM modulated signal. This signal needs to be
restored from the 14-bit signal to an 8-bit digital signal in the DSP circuit. This is called EFM demodulation. After demodulation, it is processed into a 16-bit
digital signal through error correction, interpolation, etc.
    The RF signal output by the ⑧ pin of the servo preamplifier circuit CXA1782 is coupled to the @ pin through C140, and is sent all the way to the superposition circuit, and then
to ; the other way is sent to the limiting circuit correction circuit. After buffering,
the RF signal is output from the @ pin and is integrated and filtered by R164, C142, C148, and processed into a DC voltage, which is input to the A@ pin to control the limiting
correction circuit and perform asymmetry correction on the RF signal to make the RF signal Has good symmetry. The EFM demodulation circuit
demodulates the 14-bit digital signal into an 8-bit digital signal under the control of the digital PLL circuit. In addition, the 16.934 MHz oscillation signal output from pin 8 of N203
is filtered by inductors L200, L203 and R194. C141 is added to the internal clock generator at the @ pin to generate a 4.23 MHz clock signal.
The digital PLL circuit uses the clock signal and the clock component in the RF signal to perform phase lock control to ensure the correctness of EFM demodulation.
    The 8-bit digital signal output by the EFM demodulation circuit is sent to the register, sub-code PW processor, pre-code Q processor and digital signal
output circuit respectively. The sub-code PW processor generates an 8-bit sub-code PW signal under the control of the sub-code PW clock signal input by the @ pin,
which is output (not used in this machine); the sub-code Q processor is controlled by the sub-code Q clock input by the @ pin. Under the control of the signal (SOCK) CPU @ pin output), the 8-bit
digital signal is processed into a sub-code Q signal, which is output from the @ pin and sent to the CPU ⑥ pin to control the movement.
    The 8-bit digital signal demodulated by the EFM is transmitted through the register and data bus, and then undergoes error correction processing, enters the D/A data signal
processor, and is processed into a serial data signal, which is then processed by the serial/parallel processor and output Data signal for MPEG decoding. When the @ pin (audio
data signal output mode selection switch) is high level, parallel data signal output is selected; when the @ pin is low level, the serial
data output from the @ pin sleeve (this machine is This mode) is sent to the decoding circuit via connector XP702 for further processing.