Design of a dual DSP motor control digital platform

zbz0529

Design of a dual DSP motor control digital platform [Copy link]

Abstract: Direct torque control has been applied to various control systems of synchronous and asynchronous machines. Due to the Bang-Bang control, long control cycles will lead to two prominent problems: large current and large torque pulsation. To achieve better control performance, higher requirements must be placed on the control cycle. Improving the performance of the control platform is one of the effective ways to solve these problems. TI's 2000 series DSP is a commonly used chip in the field of motor control, and the event manager designed for motor control has outstanding advantages. The 3X series DSP is a general-purpose chip with a good cost performance, floating-point operation, and fast data processing speed. For this reason, a dual-DSP system structure is adopted. Starting from the characteristics of the motor control field, the powerful control functions of TMS320LF2407A are used to focus on control work; TMS320VC33 has strong floating-point operation capabilities, and data analysis and processing are performed. The dual-port RAMCY7C025 is used to realize high-speed data exchange and communication between the two machines, so that the advantages of different MDSPs are fully reflected, and they work together to greatly improve the performance of the control platform.

Keywords: motor control; direct torque control; dual DSP; dual-port RAM; communication

　

　

0 Introduction

直接转矩控制[1]是目前广为研究的电机控制理论之一，已在异步机上取得了成功，而在同步机方面的应用也已有了一定发展[2]。由于该理论直接对转矩进行控制，故瞬态性能得到了显著的改善。但是，由于其采用的是Bang-Bang控制，控制周期过长会使电流过大；同时大周期会使转矩脉动加大。为了解决这个问题可以从控制策略上加以改进，比如采用SVM-DTC[3]来取代传统DTC方案；也可以在控制平台上加以考虑，提高处理器速度，缩短控制周期。以单个DSP为核心的控制平台（常见的芯片如TI公司的2000系列），由于既要完成复杂的算法，还要执行数据采集、控制信号输出、系统保护以及人机交互等一系列操作，无法有效地缩短控制周期。在综合考虑了各种数字信号处理器的性能之后，决定采用双DSP并行工作的体系结构；并同时考虑到该控制系统的特点，即在每个控制周期内两个DSP之间交换的信息很少，不同于诸如图像采集系统[4]那样，需要大流量的数据交换。由此采取了一系列特殊的设计思想。首先，在芯片的选型上兼顾了各自不同的特点，即专用于电机控制领域的芯片TMS320LF2407A专注于控制；高速通用数据处理芯片TMS320VC33则着眼于复杂算法的实现，从而充分利用了各自的特点。其次，针对电机控制这一特定领域，需要采集的数据相对较少，同时反馈的也只是计算结果，即PWM波发送策略，并无大量中间结果，因此，需要考虑的重点是控制方法的实现，和数据采集的实现必须占用尽可能少的资源。同时由于数据量较少，可以用较小的代价来实现数据的冗余，使得数据处理时更加灵活和方便，DSP之间并不一定保持同步工作状态。为了实现两个DSP之间的数据交换和通信，选择了双口RAM作为两者之间的媒介。并从硬件和软件上相互配合，避免存储空间争用[5]的同时，使得数据存储过程尽量少耗费各种资源。

1 Hardware system composition

The most prominent feature of TMS320LF2407A is its event manager module: there are two event managers EVA and EVB, providing 8 16-bit pulse width modulation (PWM) channels. These are designed for motor control and are quite convenient and reliable in generating PWM waves; programmable PWM dead zone control can prevent the upper and lower bridge arms from outputting trigger pulses at the same time, which will cause direct pass. At the same time, each module also provides two external pins PDPINT _A and PDPINT _B. When a low level appears on the pin, the event manager module will quickly close the corresponding PWM channel to play a protective role. The on-chip analog-to-digital conversion module provides a high-performance A/D converter for data acquisition, with a minimum conversion time of only 500ns. Since the conversion time is one of the components of the entire control cycle, fast A/D is very beneficial for shortening the control cycle.

The TMS320C3X series DSP chip is a floating-point processing chip with a good performance-price ratio and a high data processing speed. The on-chip part has a 34K×32-bit RAM, in which all data are located during program execution, so that the advantages of large data throughput and fast calculation brought by the Harvard bus structure can be fully utilized. In terms of algorithm implementation, the use of floating-point calculation format will improve the calculation accuracy; the use of programming language C will greatly improve the efficiency of program writing, which is very important for control strategies that need to be implemented with complex algorithms.

The characteristic of dual-port RAM is that it has two sets of independent address lines, data lines and control lines. The control logic contained in the chip solves three important problems: the signal relationship between processors (interrupt logic); the time relationship when two CPUs are using the same address (arbitration logic) and the hardware support for temporarily allocating a piece of memory to one side (semaphore logic), thereby ensuring the correct data and signal exchange between the two machines.

Arbitration logic (busy logic) Each CY7C025 allows two CPUs to read any storage unit at the same time (including reading the same address unit at the same time), but does not allow simultaneous writing or reading and writing the same address unit, otherwise an error will occur. The dual-port RAM already has a corresponding arbitration logic circuit to solve this problem: the first stable address port is read and written first through the arbitration logic circuit, and the internal circuit makes the BUSY signal of the other port valid, and prohibits the other party from accessing it internally until the operation of this port is completed. The BUSY signal can be used as the source of the CPU RDY signal, so that the CPU is in a waiting state.

When the dual-port RAM is used as a single chip, the problem is relatively simple. However, in modern digital systems, since the width of the data bus can often reach 32 bits or even wider, multiple dual-port RAMs are required for bit expansion. At this time, if simultaneous access occurs, multiple dual-port RAMs will be in operation. If each dual-port RAM uses its own arbitration logic as when the single chip is working, it is very likely that the first arbitration causes BUSY _L to become low, while the second arbitration causes BUSY _R to become low, so that both CPUs will be in a waiting state. In order to avoid this situation ( BUSY signal deadlock), the master-slave mode can be used so that when multiple chips work together, only the arbitration logic of the master chip is used, and the slave chip is forced to follow the master chip. The circuit connection of the master-slave mode is shown in Figure 1.

Figure 1 Master-slave connection circuit

The BUSY signal of the master chip is connected to a pull-up resistor as an output, and the BUSY signal of the slave chip is used as a write-disable input. When the master chip is in the BUSY state, the slave chip receives this state and is also in the busy state, thus avoiding the occurrence of deadlock.

Interrupt logic is another important internal circuit structure that allows dual CPUs to communicate directly through ports. The highest bit storage unit 1FFF of CY7C025 is used as the interrupt mailbox of the right port.

The second highest storage unit 1FFE is used as the interrupt mailbox of the left port. Each CPU can read the interrupt mailbox of both parties, but can only write the interrupt mailbox of the other party. When one end writes to the interrupt mailbox of the other party, the other party will generate an interrupt signal; reading its own interrupt mailbox will clear its own interrupt signal, and reading the interrupt mailbox of the other party will not clear the interrupt signal.

The semaphore communication logic can make the dual-port RAM temporarily designate a storage area for use by only one end of the CPU, which is called exclusive mode. CY7C025 is equipped with 8 semaphore latches independent of the RAM array to mark whether the dual-port RAM is in exclusive mode. Exclusive mode can also be used to avoid address arbitration problems because it is a method that prevents both sides from using the same address at the same time, which is also commonly called software arbitration.

The control platform structure block diagram is shown in Figure 2.

Figure 2 Dual DSP system structure diagram

The motor is driven by IPM, and the Hall element detects the relevant physical quantity, which is sent to the A/D converter through the signal conditioning circuit. The conversion result is stored in the dual-port RAM by LF2407A and read by VC33 for calculation. While conditioning, the protection circuit also performs corresponding detection and cuts off the trigger signal at any time when an unexpected situation occurs. VC33 analyzes and calculates the acquired data. All data processing is completed by VC33, and only the calculation results are fed back to LF2407A, which generates corresponding control signals and controls the IPM work through the interface circuit. At the same time, relevant peripheral circuits such as D/A and serial port output are reserved to realize various functions such as display, detection, and communication with other systems. LF2407A and VC33 complement each other and work in parallel. The length of the control cycle mainly depends on the algorithm implementation time. The original control software (with C32 as the control platform) takes about 100μs. After adopting the new control platform, the entire control cycle is reduced to about 20μs.

2 Dual-port RAM storage contention solution

During data communication between two machines, there is a problem of storage space contention. Common solutions are as follows.

——Hardware solution The simplest method is to use the arbitration logic inside the dual-port RAM mentioned above, requiring both CPUs to have RDY pins to insert the corresponding waiting cycle. For 8098 microcontrollers and DSPs, they all have such resources, and only require hardware support, which is relatively simple. If there is no RDY pin, such as 8031 microcontrollers, this method cannot be used.

——Interrupt scheme requires both hardware and software support. Connect the left and right interrupt signal output pins of the dual-port RAM to the external interrupt input pins of the CPU, and write the corresponding interrupt subroutine.

——Semaphore solution It also requires the support of hardware and software at the same time, which we also call software arbitration. Its steps are to apply for exclusive area, determine whether the application is successful, and release the exclusive area. Since both sides do not use the same address at the same time, contention can also be avoided.

本系统设计时综合了各种情况最后选用了硬件方案。这是因为使用中断方案软件编写复杂，频繁中断跳转在算法和控制都较复杂的情况下，对于软件的可靠性和稳定性是不利的；采用旗语方案则控制相对复杂一些；硬件方案具有简单可靠的特点，存储空间的争用完全由硬件解决，即当发生存储空间争用的时候，决定先行稳定的端口优先进行访问，另一端口则插入等待周期。由于DSP的快速性，不同于以往的单片机将产生很长的等待周期。针对本系统考虑，即使是最坏的情况：每个控制周期内传递数据8个，LF2407A一次读/写周期50ns记，共需要0.4μs。当然这完全由硬件来实现，若考虑软件上共同配合，则可以更有效地减少等待时间。而且0.4μs和20μs的控制周期相比，所占的比重非常小，并不会给系统性能带来显著影响，系统可靠性和稳定性也能够得到保证。这也正是本系统的特点所在。

3 Implementation of communication between TMS320C2407A/TMS320VC33 and CY7C025

The data bus width and address bus width of LF2407A are both 16 bits, so a single CY7C025 is sufficient. The data bus width of VC33 is 32 bits, and two CY7C025s can be used in master-slave mode to expand the width (see Figure 3), so that each time VC33 reads data, it can read the sampled data of two LF2407As at once. A single CY7C025 can also be used. Although the data width of VC33 is not fully utilized, it is relatively simple in terms of circuit design. Since the dual-port RAM in this system mainly plays the role of data transmission, it does not need to save a large number of intermediate results and used data. Therefore, the required storage space is not very large, and a single dual-port RAM is sufficient. The specific interface circuit is shown in Figure 3, and the chip select and other control signals are generated by the decoding circuit.

Figure 3 Interface circuit implementation

　

The address space allocation integrates the space resource allocation requirements of different DSPs, as shown in Table 1.

Table 1 Address space allocation table

	Starting address	End Address
LF2407A	0X8000H	0X9FFFH
VC33	010000H	011FFFH

　

4 Software Function Implementation

The key to the cooperation of dual DSPs is the close cooperation in mutual communication and data exchange, which can be accomplished through hardware arbitration circuits. However, if it is only done with hardware, as analyzed above, the waiting time is still about 0.4μs. If it is supplemented with software, the waiting time can be effectively reduced.

First, conflicts may occur when writing to the same storage unit at the same time. The following measures can be taken when writing data to avoid this situation: As shown in Figure 4, the read/write storage space is separated. Obviously, LF2407A and VC33 will not have conflicts when writing, avoiding the occurrence of waiting.

Figure 4 Separation of read/write storage space

Secondly, conflicts may occur when one reads and writes the same storage unit. Taking LF2407A writing data and VC33 reading data as an example, the above analysis of the situation where a waiting time of 0.4μs is generated is based on the following assumption: 8 data are stored in the same address unit in sequence. That is, a conflict occurs when LF2407A stores the first data, and VC33 generates a waiting time of 50ns. After the waiting time, VC33 reads the data. After that, LF2407A overwrites the previous data with the second data. The result obtained by analogy is 8×50ns=400ns. The fact is that we have enough address space to store each batch of data, and the 8 data are stored in different address spaces in sequence. At this time, the situation is as follows: a conflict occurs when LF2407A stores the first data, and VC33 generates a waiting time of 50ns. After the waiting time, VC33 reads the data. At the same time, LF2407A also starts to write the second data in the next storage unit. Both are carried out at the same time. As long as we ensure that when VC33 finishes reading, LF2407A has finished writing the second data, there will be no conflict. For this example, since the two times are different (LF2407A is 50ns, VC33 is 13.3ns), VC33 reads faster, and as long as a 40ns loop is added in the software writing, the above requirements can be met. When the read/write is reversed, there is no such situation and they can cooperate smoothly. In this way, the final result is only an increase of 50ns waiting cycle, which is completely acceptable for this system.

Since the two DSPs do not work synchronously, LF2407A can sample and save as much data as possible, and VC33 only uses the latest data for calculation, thus ensuring data redundancy. The program flow is shown in Figure 5.

(a) LF2407A flow chart

(b) VC33 flow chart

Figure 5 Flowchart of dual-machine communication using dual-port RAM

5 Conclusion

The dual DSP control system comprehensively utilizes the advantages and strengths of TMS320LF2407A and TMS320VC33 chips. The two chips have clear division of labor in control and calculation and work in parallel. When using dual-port RAM to realize the exchange of data and information, in view of the relatively small number of sampled data in the motor control system, the hardware and software cooperate with each other. While solving the contention for storage space, it also solves the waste of resources such as waiting time and avoids the software instability caused by interrupts during data exchange. The coordination between the two chips is achieved, which greatly shortens the control cycle and improves the performance of the control platform. For the direct torque control of low-inductance synchronous motors, the problem of excessive current rise caused by too long a control cycle can be well solved, and the torque pulsation is also significantly reduced.