Download>Category>FPGA/CPLD>How to use Xilinx FPGA global clock resources

doc

How to use Xilinx FPGA global clock resources

2013-09-19
24.5KB
Points it Requires : 2

repReport

Document Introduction
You Might Like
Recommended Downloads

At present, it is generally recommended to use synchronous timing circuits for large designs. Synchronous timing circuits are based on clock trigger edge design and have higher requirements for the clock period, duty cycle, delay and jitter. In order to meet the requirements of synchronous timing design, global clock resources are generally used in FPGA design to drive the master clock of the design to achieve the lowest clock jitter and delay. FPGA global clock resources are generally implemented using full copper layer technology, and dedicated clock buffers and drive structures are designed to minimize the delay and jitter of the global clock reaching all configurable units (CLBs), I/O units (IOBs) and selective block RAMs (Block Select RAM) inside the chip. In order to meet the needs of complex designs, the number of dedicated clock resources and digital delay-locked loops (DLLs) integrated in Xilinx FPGAs continues to increase. The latest Virtex II devices can provide up to 16 global clock input ports and 8 digital clock management modules (DCMs). Primitives related to global clock resources Commonly used Xilinx device primitives related to global clock resources include: IBUFG, IBUFGDS, BUFG, BUFGP, BUFGCE, BUFGMUX, BUFGDLL and DCM, as shown in Figure 1.

unfold

You Might Like

Uploader

: baidu_linker

Recommended ContentMore

Open source project More

Popular Components

Searched by Users

Just Take a LookMore

What is the relationship between STM32 and IoT?
Speaking of STM32, people in the industry should know that this is a series of microcontrollers with super cost-effectiveness. It is extremely powerful, with excellent performance in power consumption
How to make aluminum conductors contact firmly
During the holiday, I saw a friend repairing the electrical wires at his rental house. The electrical wires in this old house built 30 years ago were actually made of aluminum wires. The joints were s
About the status of STC microcontroller IO port
I just joined a company that makes smart home products and only uses Hongjing 51 microcontrollers. I haven't worked on it for a long time, and today I encountered a problem that I had never encountere
Nand flash driver working principle
Before introducing how to write Nand Flash driver, we should first understand the general process of the driver related to Nand Flash in the whole system. In this way, the mechanism can be more clear
Several questions in the chip manual
[color=#333333][font="][If you don't understand, ask] [/font][/color][color=#333333][font="]This is part of the datasheet of the power conversion chip MP2315 [/font][/color] [color=#333333][font="]I h
Southchip SC8905 EVM evaluation report summary
There is a new board~~ Take a look~~
LSM6DSOX First Experience
About CC2640 power consumption test problem
An experienced person tells you how to choose a common mode noise filter

Trending Downloads

Trending ArticlesMore

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

About Us Customer Service Contact Information Datasheet Sitemap LatestNews

Room 1530, 15th Floor, Building B, No.18 Zhongguancun Street, Haidian District, Beijing, Postal Code: 100190 China Telephone: 008610 8235 0740

Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号京ICP备10001474号-1 电信业务审批[2006]字第258号函

京公网安备 11010802033920号

×