[Reading] "RISC-V Open Architecture Design" 3. Multiplication and Division Instruction Set RV32M

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[Reading] "RISC-V Open Architecture Design" 3. Multiplication and Division Instruction Set RV32M [Copy link]

This post briefly talks about multiplication and division in RV. RV32M is a standard extended instruction set in the RISC-V architecture, which adds multiplication and division operations to the RV32I basic integer instruction set. The RV32M extension contains a series of instructions for performing multiplication, division, and related operations, which are very useful for performing arithmetic-intensive tasks. As an extended instruction set of RV32I, the multiplication and division instruction set (RV32M) has relatively few instructions, as shown in the figure:

Instruction Format

RV32M instructions typically use the R-type (Register) format, which contains three register operands (rs1, rs2, and rd), and an opcode to indicate the specific multiplication or division operation to be performed.

I recommend reading Lao Lang’s post for this usage: https://www.cnblogs.com/mikewolf2002/p/9872287.html It is written in more detail, so I will not repeat it here

Instruction List

Multiplication Instructions

mul rd, rs1, rs2, the usage is register [rs2] multiplied by register [rs1], and the product is written to register x[rd].

The multiplication instructions are:

mul

: Unsigned multiplication, the result is 32 bits.

mulh

: Unsigned multiplication, the high 32 bits of the result.

mulhsu

: Multiplication when one operand is unsigned and the other is signed, the high 32 bits of the result are taken into account.

mulhu

: Both operands are unsigned multiplication, and the high 32 bits of the result are used.

mulhusu

: 32-bit signed-unsigned multiplication, the result is 32 bits. This is special: x[rs2] is an unsigned number, and the rest is the same as mulhu

Division Instructions

div rd, rs1, rs2 divides register x[rs1] by register x[rs2], rounding towards zero, treating the numbers as two's complement, and writing the quotient to x[rd].

The division instructions are:

div

: Unsigned division, the result is 32 bits.

divu

: Signed division, the result is 32 bits.

rem

: The remainder of unsigned division, the result is 32 bits.

remu

: The remainder of a signed division, the result is 32 bits.

Conclusion

Unlike ARM, which has only had multiplication instructions for a long time, the division instruction was not added until 2005. The multiplication instruction is used to perform fast hardware multiplication operations, which is essential for digital signal processing, graphics processing, and other applications that require a large number of multiplications. Moreover, RV32M, as an extended instruction, can be selectively added to RV32I, which means it can be omitted in scenarios where multiplication and division operations are not required to save hardware resources.