[Analysis of the topic of the college electronic competition] - 2016 Jiangsu Province TI Cup F "Bit Synchronous Clock Extraction Circuit"

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[Analysis of the topic of the college electronic competition] - 2016 Jiangsu Province TI Cup F "Bit Synchronous Clock Extraction Circuit" [Copy link]

 

topic

1. Mission

Design and produce a circuit that can extract the bit synchronization clock from the binary baseband signal, and can measure and display the extracted bit synchronization clock frequency. The block diagram of the designed and produced circuit is shown in the figure below.

II. Requirements

( 1 ) Design and manufacture a "baseband signal generation circuit" to simulate the non-logic level baseband signal sampled and judged at the receiving end of a binary digital communication system. Requirements:

1) The feedback characteristic polynomial (primitive polynomial) of the m-sequence generator is f ( x ) = x ⁸ + x ⁴ + x ³ + x ² +1 , and its sequence output signal and external input ck signal are both TTL levels.

2) Design and manufacture an infinite gain multi-channel negative feedback second-order active low-pass filter with a 3dB cutoff frequency of 300kHz to filter the m- sequence output signal and attenuate it into a baseband analog signal ( A signal) with a peak-to-peak value of 0.1V .

( 2 ) when the frequency of the ck signal input to the m sequence generator is 200 kHz , design and manufacture a circuit that can extract the bit synchronization clock ( B signal) from the A signal and digitally display the frequency of the synchronization clock

( 3 ) The bit synchronization clock extraction circuit is improved. When the frequency of the ck signal input to the m- sequence generator varies between 200kHz and 240kHz , the bit synchronization clock can be adaptively extracted from the A signal and the frequency of the synchronization clock can be digitally displayed.

( 4 ) Reduce the pulse phase jitter Δ of the bit synchronization clock ( B signal) , requiring Δ _max ≤ 10% of one bit synchronization clock cycle .

( 5 ) Others.

3. Description

( 1 ) Bit synchronization is the basic synchronization technology of digital synchronous transmission. It refers to the signal synchronization state in which the bit synchronization clock extracted by the receiving end is strictly equal to the bit clock of the transmitting end in frequency and the phase difference is fixed. The receiving end bit clock needs to be extracted from the received baseband data sequence and will be used as the sampling decision pulse of the receiving end and further realize other synchronization. The "bit" in the digital communication system refers to the most basic code element. The transmitting end bit clock (the external input clock ck of the m- sequence generator in the title ) is the code element clock of the data sequence.

( 2 ) The "baseband signal generation circuit" must be made into a separate circuit board and can only be connected to the bit synchronization clock extraction circuit using two output signal lines ( A signal line and ground line).

( 3 ) Infinite gain multi-channel negative feedback second-order active low-pass filter type (such as Chebyshev type or Butterworth type) is not limited.

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Topic analysis and solution design

This topic has three parts, as follows:

1. m- sequence generator.

It can be realized by using shift register plus XOR gate. The figure below is the schematic diagram of the m- sequence generator implemented according to ^{the primitive polynomial given in the question. The three XOR gates on the right implement the bitwise addition of the outputs of the four registers} x8 , x4 , x3 , and ^{x2 in the primitive polynomial. The} XOR gate on the far left and the 8- input NOR gate implement the all-zero exclusion circuit ^{. Without this part of the circuit,} the system will be locked when all register bits output " 0 ".

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2. Active low-pass filter and attenuator.

In a real digital communication system, this low-pass filter between the digital sequence generator and the receiver actually has two parts: the first part is a pre-modulation filter inserted in the digital modulation circuit to suppress the out-of-band power radiation caused by the high-order harmonics of the rectangular pulse signal. Usually, this filter is a low-pass filter with a flat delay characteristic, such as a Gaussian filter. The second part is not an actual filter circuit, but a communication channel with a low-pass characteristic. In this question, a low-pass filter is used to simulate the above two parts in actual communication, and the cutoff frequency is specified to be 300kHz , 2nd order, and the circuit type is an infinite gain multi-feedback filter. In order to reduce the overshoot of the pulse response and obtain a flatter delay characteristic, a Bessel or Butterworth filter can be selected, and the Q value should not be greater than 0.7 .

Since the filter cutoff frequency is 300kHz , all high-order harmonics in the signal ( 200kHz~240kHz ) are filtered out, and the signal waveform after the low-pass filter is similar to a sine wave, but not a periodic waveform.

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3. Synchronous clock extraction circuit.

The circuit should contain three parts. The first part is a low noise amplifier, which amplifies the 0.1V sine wave-like signal to a suitable level and then uses a zero-crossing comparator to shape it into a rectangular pulse. The second part is a synchronous signal extraction circuit based on a phase-locked loop. The third part is a frequency display circuit completed by a single-chip microcomputer, which also has the function of controlling the entire system.

The synchronization signal extraction circuit in the above circuit is the core of this problem. Its basic structure is an edge detection circuit and a phase-locked loop.

The edge detection circuit shapes the leading and trailing edges of the input rectangular pulse signal into a pulse signal. The specific structure and signal waveform are as follows:

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The phase-locked loop recovers the continuous synchronization signal based on the pulse signal generated by the edge detection circuit. The specific design requirements are analyzed as follows:

In order to obtain the best capture range, the phase-locked loop uses PFD phase detection. The controllable oscillation frequency range of the VCO in the phase-locked loop must be greater than the frequency range of the input signal (in this question, the frequency range of the clock signal CK ).

The loop filter design in the bit synchronization circuit in this question has certain particularities. In addition to the damping factor usually being around 0.7 , its natural frequency is also related to the characteristics of the m- sequence.

The m- sequence generator generates a pseudo-random code. The characteristic of this code is that the m- sequence generated by the n- stage shift register can generate a code sequence with a maximum length of 2n ^- 1 bits, which is 28-1 =255 bits in this problem ^, in which the number of 0s and 1s is basically equal ( the number of 1s in one cycle is one more than the number of 0s ). Continuous 1s or continuous 0s are called runs, and the number of 1s or 0s in a run is called the run length. There are a total of 2n ^-1 runs in a code sequence cycle of an n - stage m -sequence, of which runs of length 1 account for 1/2 of the total number of runs , runs of length 2 account for 1/4 of the total number of runs , … , and runs of length k account for 1/(2k) of the total number of runs . And in a run of length k , the number of runs of consecutive 0s and consecutive 1s each accounts for half. The longest run is n all 1s and n-1 all 0s .

When a run of length greater than 1 appears in the m- sequence, the edge pulse signal output by the edge extraction circuit will be missing because the input signal remains continuous for more than 1 clock cycle. The longest run of the m- sequence in this question is 8 1s , which means that the phase-locked loop may not receive the input edge pulse signal within 8 clock cycles.

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The figure below is a schematic diagram of the working status of the phase detector and loop filter. The PFD phase detector is triggered by the rising edge of the input signal pulse. In the normal locked state, the output of the phase-locked loop is at the same frequency as the input, that is, the PFD will simultaneously obtain the two rising edges of the input signal pulse and the output feedback of the phase-locked loop, and its output is in a high-impedance state (dashed line in the figure), and the output of the loop filter remains unchanged.

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Once the input is continuously 1 or 0 , the input signal edge pulse is missing, and the PFD only has a feedback signal but no input signal. In this case, the output of the PFD will directly jump to its output high level and remain until the next edge pulse appears. In this case, the loop filter receives a step input voltage, and its output will rise exponentially. For a lead-lag loop filter, its output voltage is

Where V _S is the step input voltage seen by the loop filter, and V (0) is the loop filter output voltage before the step input occurs.

For the convenience of analysis, some reasonable approximations are made to the above exponential equation.

Considering that the time t for continuous 1 or continuous 0 is usually much smaller than the time constant of the loop filter (otherwise the phase-locked loop will not be able to lock), that is, t << ( R ₁ + R ₂ ) C , the above exponential can be expanded using a power series and its linear term is taken, so we have

According to the characteristics of most phase-locked loop loop filters, R ₂ << R ₁ , the above equation can be further simplified to

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Therefore, when the input signal is continuously 1 or 0 , it is approximately considered that the output voltage of the loop filter rises linearly after the step voltage input. Under this rising voltage control, the output phase of the VCO is

So after the step occurs, the output phase of the VCO will continue to advance, and the output phase change at time t is

This phase change is the output phase jitter of the phase-locked loop.

As can be seen from the previous diagram, if n consecutive 1s or 0s are input , the step pulse occurs at the end of the first bit period, and the maximum phase jitter occurs after the nth bit period . Therefore, t=(n-1)Ts when the maximum phase jitter occurs , that is,

It can be seen that the output phase jitter of the phase-locked loop is related to the length n of the continuous 1 or continuous 0 (run) of the input signal, and is basically in a square relationship. Since n = 1 is the input continuous wave (carrier), the bit stream containing the modulation information n ≥ 2. Under the condition that other parameters remain unchanged, n = 2 has the smallest output phase jitter.

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It is known that the natural frequency of the lead-lag loop filter is

So the previous relationship can also be written as

The natural frequency that meets the output phase jitter requirement is

The above formula is the natural frequency design constraint under this input signal condition. Among them, n is the number of consecutive 1 or 0 , Δφ _max is the maximum phase jitter, Kd is the phase-detection gain, VS is the step voltage of the input loop filter, and _{Ts is the} normal synchronization pulse period.

Since the output of the phase detector is high impedance before the step input voltage occurs, and the input resistance of the VCO behind the loop filter _is also _high , it can be considered that no current flows through R1 and R2 , so the input voltage and output voltage of the loop filter are equal to the voltage on the capacitor C before the step occurs. Therefore, the step input voltage of the loop filter V _S = V _H - V (0) is obtained . Normally, the output voltage of the loop filter before the step input occurs V (0) ≈ V _H /2 , so V _S = V _H - V (0) ≈ V _H /2 . The phase detector gain of the PFD K _d = V _H /4 π , so the above constraints can also be approximated as

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Back to the question, the pulse phase jitter is required to be less than 10% of one bit synchronization clock period , that is, Δ φ _max =2π/10 . The maximum run length of the m- sequence given in the question is n =8 , _and the maximum synchronization signal period is _Ts = 1/(2 ^× 105 ) . Substituting these data, we can get the constraint condition of the natural frequency as ωn <9035 .

In carrier synchronization circuits, there is usually no missing input signal pulse, only a large amount of noise will affect the output phase jitter, so the natural frequency must be much lower than the input signal frequency. In addition, the order of the phase-locked loop can be increased to filter high-frequency noise to reduce the output phase jitter caused by noise.

However, there may be missing input signal pulses in the bit synchronization circuit. In this case, the natural frequency constraint condition should be determined by the output phase jitter as discussed above. It can be understood that missing input signal pulses is equivalent to the presence of a spectrum component lower than the synchronization signal in the input signal. In this case, increasing the order of the phase-locked loop is powerless, so it is necessary to rely on reducing the closed-loop bandwidth of the phase-locked loop to solve the phase jitter caused by it.

Of course, lowering the natural frequency will inevitably increase the capture time. So if the system still has requirements for capture time, it may be necessary to make a reasonable compromise between phase jitter and capture time, or use other auxiliary circuits to improve capture capability, such as scanning capture circuits.

The m- sequence in this question is actually simulating the bit stream of the original information, and the run length of the original information bit stream is uncertain. In that case, it is very difficult to control the output phase jitter of the phase-locked loop. Therefore, in actual digital signal transmission, a certain encoding method must be used to control the run length of the encoded bit stream. For example, the widely used Manchester code has a maximum continuous 1 or continuous 0 length of only 2 clock cycles. Obviously, this encoding can achieve the minimum output phase jitter.

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illustrate

This analysis involves many basic knowledge points in phase-locked loop design. If you are not familiar with them, you can refer to my article "Talking about Phase-Locked Loops - An Overview of Design Steps" https://en.eeworld.com/bbs/thread-607483-1-1.html

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